zynq: fix UART output on zynq boards

2017-03-09 13:03:22 +01:00
parent ae9659f456
commit 0830b35401
1 changed files with 2 additions and 1 deletions
--- a/src/core/include/spec/xilinx_uartps_1/serial.h
+++ b/src/core/include/spec/xilinx_uartps_1/serial.h
@@ -16,6 +16,7 @@

 /* core includes */
 #include <board.h>
+#include <platform.h>

 /* Genode includes */
 #include <drivers/uart_base.h>
@@ -36,7 +37,7 @@ class Genode::Serial : public Xilinx_uartps_base
 		 */
 		Serial(unsigned const baud_rate)
 		:
-			Xilinx_uartps_base(Board::UART_1_MMIO_BASE,
+			Xilinx_uartps_base(Platform::mmio_to_virt(Board::UART_1_MMIO_BASE),
 			                   Board::UART_CLOCK, baud_rate)
 		{ }
 };