From 0830b354010413c112c42bc3871a5903a6561bf4 Mon Sep 17 00:00:00 2001
From: Johannes Schlatow <schlatow@ida.ing.tu-bs.de>
Date: Thu, 9 Mar 2017 13:03:22 +0100
Subject: [PATCH] zynq: fix UART output on zynq boards

---
 src/core/include/spec/xilinx_uartps_1/serial.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/core/include/spec/xilinx_uartps_1/serial.h b/src/core/include/spec/xilinx_uartps_1/serial.h
index 292246e..03f20b7 100644
--- a/src/core/include/spec/xilinx_uartps_1/serial.h
+++ b/src/core/include/spec/xilinx_uartps_1/serial.h
@@ -16,6 +16,7 @@
 
 /* core includes */
 #include <board.h>
+#include <platform.h>
 
 /* Genode includes */
 #include <drivers/uart_base.h>
@@ -36,7 +37,7 @@ class Genode::Serial : public Xilinx_uartps_base
 		 */
 		Serial(unsigned const baud_rate)
 		:
-			Xilinx_uartps_base(Board::UART_1_MMIO_BASE,
+			Xilinx_uartps_base(Platform::mmio_to_virt(Board::UART_1_MMIO_BASE),
 			                   Board::UART_CLOCK, baud_rate)
 		{ }
 };