FOC/L4RE: Add license

Second CPU is up and receives timer interrupts. Caches are still disabled.

.gitignore

@@ -0,0 +1,6 @@
+*~
+*.orig
+*.swp
+*.rej
+
+

COPYING-GPL-2

@@ -0,0 +1,349 @@
+
+  NOTE! This License shall not affect user programs that use the micro-kernel
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+
+-----------------------------------------------------------------------
+
+
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
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+Public License instead of this License.

kernel/fiasco/src/Kconfig

@@ -85,7 +85,7 @@ config ABI_VF
 
 config PF_ARM_MP_CAPABLE
 	bool
-	default y if ARM_MPCORE || ARM_CORTEX_A9
+	default y if ARM_MPCORE || ARM_CORTEX_A9 || ARM_CORTEX_A15
 
 config CAN_ARM_CPU_SA1100
 	bool
@@ -114,6 +114,9 @@ config CAN_ARM_CPU_CORTEX_A8
 config CAN_ARM_CPU_CORTEX_A9
 	bool
 
+config CAN_ARM_CPU_CORTEX_A15
+	bool
+
 config CAN_ARM_CACHE_L2CXX0
 	bool
 
@@ -161,6 +164,10 @@ config ARM_CORTEX_A9
 	bool "ARM Cortex-A9 CPU"
 	depends on CAN_ARM_CPU_CORTEX_A9
 
+config ARM_CORTEX_A15
+	bool "ARM Cortex-A15 CPU"
+	depends on CAN_ARM_CPU_CORTEX_A15
+
 config IA32_486
 	bool "Intel 80486"
 	depends on IA32
@@ -676,6 +683,14 @@ config POWERSAVE_GETCHAR
 	  prevent some P4 processors from being overheated. This option
 	  requires a working timer IRQ to wakeup getchar periodically.
 
+config USER_SINGLE_STEP
+	bool "Enable user level single stepping support"
+	depends on IA32
+	default n
+	help
+	  This option enables single stepping of user level applications outside of
+	  JDB.
+
 choice
 	prompt "Warn levels"
 	default WARN_WARNING
@@ -755,7 +770,7 @@ config ARM_V6
 	def_bool y if ARM_1136 || ARM_1176 || ARM_MPCORE
 
 config ARM_V7
-	def_bool y if ARM_CORTEX_A8 || ARM_CORTEX_A9
+	def_bool y if ARM_CORTEX_A8 || ARM_CORTEX_A9 || ARM_CORTEX_A15
 
 config ARM_V6PLUS
 	def_bool y if ARM_V6 || ARM_V7

kernel/fiasco/src/Modules.arm

@@ -29,6 +29,7 @@ PREPROCESS_PARTS-$(CONFIG_ARM_1176)                 += arm1176
 PREPROCESS_PARTS-$(CONFIG_ARM_MPCORE)               += mpcore
 PREPROCESS_PARTS-$(CONFIG_ARM_CORTEX_A8)            += armca8
 PREPROCESS_PARTS-$(CONFIG_ARM_CORTEX_A9)            += armca9
+PREPROCESS_PARTS-$(CONFIG_ARM_CORTEX_A15)           += armca15
 PREPROCESS_PARTS-$(CONFIG_ARM_TZ)                   += tz
 PREPROCESS_PARTS-$(CONFIG_ARM_1176_CACHE_ALIAS_FIX) += arm1176_cache_alias_fix
 PREPROCESS_PARTS-$(CONFIG_ARM_CPU_ERRATA)           += arm_cpu_errata

kernel/fiasco/src/drivers/arm/mmu-arm.cpp

@@ -171,7 +171,7 @@ FIASCO_NOINLINE void Mmu<Flush_area, Ram>::inv_dcache(void const *start, void co
 }
 
 //-----------------------------------------------------------------------------
-IMPLEMENTATION [arm && (mpcore || arm1136 || arm1176 || armca8 || armca9)]:
+IMPLEMENTATION [arm && (mpcore || arm1136 || arm1176 || armca8 || armca9 || armca15)]:
 
 IMPLEMENT inline
 template< unsigned long Flush_area, bool Ram >
@@ -303,7 +303,7 @@ void Mmu<Flush_area, Ram>::flush_dcache()
 
 
 //-----------------------------------------------------------------------------
-INTERFACE [arm && (armca8 || armca9)]:
+INTERFACE [arm && (armca8 || armca9 || armca15)]:
 
 EXTENSION class Mmu
 {
@@ -344,7 +344,7 @@ EXTENSION class Mmu
 };
 
 //-----------------------------------------------------------------------------
-INTERFACE [arm && armca9]:
+INTERFACE [arm && (armca9 || armca15)]:
 
 EXTENSION class Mmu
 {
@@ -362,7 +362,7 @@ EXTENSION class Mmu
 };
 
 //-----------------------------------------
-IMPLEMENTATION [arm && (armca8 || armca9)]:
+IMPLEMENTATION [arm && (armca8 || armca9 || armca15)]:
 
 PRIVATE
 template< unsigned long Flush_area, bool Ram >

kernel/fiasco/src/drivers/arm/processor-arm.cpp

@@ -222,7 +222,7 @@ void Proc::halt()
 }
 
 //----------------------------------------------------------------
-IMPLEMENTATION[arm && (armca8 || armca9)]:
+IMPLEMENTATION[arm && (armca8 || armca9 || armca15)]:
 
 IMPLEMENT static inline
 void Proc::pause()

kernel/fiasco/src/jdb/jdb_kobject_names.cpp

@@ -43,7 +43,7 @@ IMPLEMENTATION:
 
 enum
 {
-  Name_buffer_size = 8192,
+  Name_buffer_size = 4*8192,
   Name_entries = Name_buffer_size / sizeof(Jdb_kobject_name),
 };
 

kernel/fiasco/src/kern/arm/bootstrap.cpp

@@ -25,7 +25,7 @@ set_asid()
 {}
 
 //---------------------------------------------------------------------------
-IMPLEMENTATION [arm && armv6plus && (mpcore || armca9)]:
+IMPLEMENTATION [arm && armv6plus && (mpcore || armca9 || armca15)]:
 
 enum
 {
@@ -33,7 +33,7 @@ enum
 };
 
 //---------------------------------------------------------------------------
-IMPLEMENTATION [arm && armv6plus && !(mpcore || armca9)]:
+IMPLEMENTATION [arm && armv6plus && !(mpcore || armca9 || armca15)]:
 
 enum
 {
@@ -80,6 +80,19 @@ IMPLEMENTATION [arm && !arm1176_cache_alias_fix]:
 
 static void do_arm_1176_cache_alias_workaround() {}
 
+//---------------------------------------------------------------------------
+IMPLEMENTATION [arm && exynos5_arndale]:
+
+static inline void supervisor_mode()
+{
+  asm volatile ("cps #19");
+}
+
+//---------------------------------------------------------------------------
+IMPLEMENTATION [arm && !exynos5_arndale]:
+
+static inline void supervisor_mode() { }
+
 //---------------------------------------------------------------------------
 IMPLEMENTATION [arm]:
 
@@ -145,6 +158,8 @@ extern "C" void bootstrap_main()
   extern char kernel_page_directory[];
   void *const page_dir = kernel_page_directory + Virt_ofs;
 
+  supervisor_mode();
+
   Address va, pa;
   // map sdram linear from 0xf0000000
   for (va = Mem_layout::Map_base, pa = Mem_layout::Sdram_phys_base;

kernel/fiasco/src/kern/arm/bsp/exynos5/Kconfig

@@ -0,0 +1,15 @@
+# PF: EXYNOS5
+# PFDESCR: Samsung Exynos5
+# PFDEPENDS: ARM
+
+choice
+	prompt "Exynos5 Platform"
+	default PF_EXYNOS5_ARNDALE
+
+config PF_EXYNOS5_ARNDALE
+	bool "Samsung Arndale"
+	depends on PF_EXYNOS5
+	select CAN_ARM_CPU_CORTEX_A15
+	help
+	  Choose for Arndale board platform.
+endchoice

kernel/fiasco/src/kern/arm/bsp/exynos5/Modules

@@ -0,0 +1,25 @@
+# vim:set ft=make:
+
+SUBSYSTEMS       += LIBUART
+OBJECTS_LIBUART  += uart_s3c2410.o
+PREPROCESS_PARTS += exynos5 libuart
+PREPROCESS_PARTS += $(if $(CONFIG_PF_EXYNOS5_ARNDALE), exynos5_arndale pic_gic)
+
+CONFIG_KERNEL_LOAD_ADDR := 0x40000000
+#no memory mapped SCU on exynos5
+MPCORE_PHYS_BASE        := 0x0 
+
+INTERFACES_KERNEL+= $(if $(CONFIG_PF_EXYNOS5_ARNDALE),gic)
+
+bootstrap_IMPL        += bootstrap-arm-exynos5
+clock_IMPL            += clock-generic
+config_IMPL           += config-arm-exynos5
+kernel_uart_IMPL      += kernel_uart-arm-exynos5
+mem_layout_IMPL       += mem_layout-arm-exynos5
+pic_IMPL              += pic-gic pic-arm-gic-exynos5
+platform_control_IMPL += platform_control-arm-exynos5
+reset_IMPL            += reset-arm-exynos5
+timer_IMPL            += timer-arm-exynos5
+timer_tick_IMPL       += timer_tick-multi-vector
+uart_IMPL             += uart-arm-exynos5
+warn_IMPL             += warn warn-exynos5

kernel/fiasco/src/kern/arm/bsp/exynos5/bootstrap-arm-exynos5.cpp

@@ -0,0 +1,20 @@
+INTERFACE [arm && exynos5]:
+
+enum {
+  Cache_flush_area = 0,
+};
+
+IMPLEMENTATION [arm && exynos5]:
+
+#include "mem_layout.h"
+#include "io.h"
+
+void
+map_hw(void *pd)
+{
+  map_dev<Mem_layout::Devices1_phys_base>(pd, 1);
+  map_dev<Mem_layout::Devices2_phys_base>(pd, 2);
+  map_dev<Mem_layout::Devices3_phys_base>(pd, 3);
+  map_dev<Mem_layout::Devices4_phys_base>(pd, 4);
+  map_dev<Mem_layout::Devices5_phys_base>(pd, 5);
+}

kernel/fiasco/src/kern/arm/bsp/exynos5/config-arm-exynos5.cpp

@@ -0,0 +1,3 @@
+INTERFACE[arm && exynos5_arndale]: //-----------------------------------------
+#define TARGET_NAME "ArndaleBoard"
+

kernel/fiasco/src/kern/arm/bsp/exynos5/kernel_uart-arm-exynos5.cpp

@@ -0,0 +1,12 @@
+INTERFACE:
+
+// On ARM the MMIO for the uart is accessible before the MMU is fully up
+EXTENSION class Kernel_uart { enum { Bsp_init_mode = Init_before_mmu }; };
+
+IMPLEMENTATION [arm && exynos5 && serial]:
+
+IMPLEMENT
+bool Kernel_uart::startup(unsigned, int)
+{
+  return Uart::startup();
+}

kernel/fiasco/src/kern/arm/bsp/exynos5/mem_layout-arm-exynos5.cpp

@@ -0,0 +1,32 @@
+INTERFACE [arm && exynos5]:
+
+EXTENSION class Mem_layout
+{
+public:
+  enum  Phys_layout_exynos5 : Address {
+    Devices1_phys_base = 0x10000000,
+    Devices2_phys_base = 0x12c00000,
+    Devices3_phys_base = 0x10400000,
+    Devices4_phys_base = 0x12d00000,
+    Devices5_phys_base = 0x02000000,
+  };
+
+  enum Virt_layout_exynos5 : Address {
+    Uart2_map_base  = Devices2_map_base + 0x20000,
+  };
+};
+
+INTERFACE [arm && exynos5_arndale]:
+
+EXTENSION class Mem_layout
+{
+public:
+  enum Virt_layout_exynos5_arndale : Address {
+    Uart_base         = Uart2_map_base,
+    Sdram_phys_base   = 0x40000000,
+    Gic_cpu_map_base  = Devices3_map_base + 0x82000,
+    Gic_dist_map_base = Devices3_map_base + 0x81000,
+    Timer_map_base    = Devices4_map_base + 0xd0000,
+  };
+};
+

kernel/fiasco/src/kern/arm/bsp/exynos5/pic-arm-gic-exynos5.cpp

@@ -0,0 +1,39 @@
+INTERFACE [arm && pic_gic exynos5]:
+
+#include "gic.h"
+
+IMPLEMENTATION [arm && pic_gic exynos5]:
+
+#include "irq_mgr_multi_chip.h"
+#include "kmem.h"
+
+IMPLEMENT FIASCO_INIT
+void
+Pic::init()
+{
+  typedef Irq_mgr_multi_chip<8> M;
+
+  M *m = new Boot_object<M>(16);
+
+  gic.construct(Kmem::Gic_cpu_map_base, Kmem::Gic_dist_map_base);
+  m->add_chip(0, gic, gic->nr_irqs());
+
+  Irq_mgr::mgr = m;
+}
+
+IMPLEMENT inline
+Pic::Status Pic::disable_all_save()
+{ return 0; }
+
+IMPLEMENT inline
+void Pic::restore_all(Status)
+{}
+
+// ------------------------------------------------------------------------
+IMPLEMENTATION [arm && mp && pic_gic && exynos5]:
+
+PUBLIC static
+void Pic::init_ap(unsigned)
+{
+  gic->init_ap();
+}

kernel/fiasco/src/kern/arm/bsp/exynos5/platform_control-arm-exynos5.cpp

@@ -0,0 +1,22 @@
+INTERFACE [arm && mp && exynos5]:
+#include "types.h"
+
+IMPLEMENTATION [arm && mp && exynos5]:
+
+#include "io.h"
+#include "kmem.h"
+#include "stdio.h"
+
+
+PUBLIC static
+void
+Platform_control::boot_ap_cpus(Address phys_tramp_mp_addr)
+{
+  // Write start address to iRam base (0x2020000). This is checked by the app
+  // cpus wihtin an wfe (wait-for event) loop.
+
+  Io::write<Mword>(phys_tramp_mp_addr, Kmem::Devices5_map_base + 0x20000); 
+  // wake-up cpus
+  asm volatile("dsb; sev" : : : "memory");
+}
+

kernel/fiasco/src/kern/arm/bsp/exynos5/reset-arm-exynos5.cpp

@@ -0,0 +1,15 @@
+IMPLEMENTATION [arm && exynos5]:
+
+#include "io.h"
+#include "kmem.h"
+
+void __attribute__ ((noreturn))
+platform_reset(void)
+{
+  enum { PRM_RSTCTRL = Kmem::Devices1_map_base + 0x40400 };
+
+  Io::write<Mword>(1, PRM_RSTCTRL);
+
+  for (;;)
+   ;
+}

kernel/fiasco/src/kern/arm/bsp/exynos5/timer-arm-exynos5.cpp

@@ -0,0 +1,88 @@
+INTERFACE [arm & exynos5]:
+
+#include "kmem.h"
+#include "processor.h"
+
+EXTENSION class Timer
+{
+public:
+  enum {
+    BASE      = Kmem::Timer_map_base,
+    CFG0      = BASE,
+    CFG1      = BASE + 0x4,
+    TCON      = BASE + 0x8,
+    TCNTB0    = BASE + 0xc,
+    TCMPB0    = BASE + 0x10,
+    TINT_STAT = BASE + 0x44,
+    ONE_MS    = 33000, /* HZ */
+  };
+
+    static unsigned irq() { return  68 + Proc::cpu_id(); }
+};
+
+IMPLEMENTATION [arm && exynos5]:
+
+#include "cpu.h"
+#include "io.h"
+#include "irq_mgr.h"
+#include "mmu.h"
+
+IMPLEMENT inline
+void
+Timer::update_one_shot(Unsigned64 wakeup)
+{
+  (void)wakeup;
+}
+
+static inline
+Mword
+tcon_to_timer(Mword val, unsigned cpu_id)
+{
+  return  cpu_id == 0 ? val : (val << (4 + (4 * cpu_id)));
+}
+
+IMPLEMENT
+void Timer::init(unsigned)
+{
+  unsigned cpu_id = Proc::cpu_id();
+
+  if (Cpu::boot_cpu()->phys_id() == cpu_id)
+    {
+      // prescaler to one
+      Io::write<Mword>(0x101, CFG0);
+      // divider to 1
+      Io::write<Mword>(0x0, CFG1);
+    }
+  // program 1ms
+  Mword offset = 0xc * cpu_id;
+  Io::write<Mword>(ONE_MS, TCNTB0 + offset);
+  Io::write<Mword>(0x0, TCMPB0 + offset);
+
+  // enable IRQ
+  Io::set<Mword>(0x1 << cpu_id, TINT_STAT);
+
+  // load and start timer in invterval mode
+  Mword tcon = Io::read<Mword>(TCON);
+  Io::write<Mword>(tcon | tcon_to_timer(0xa, cpu_id), TCON);
+  Io::write<Mword>(tcon | tcon_to_timer(0x9, cpu_id), TCON);
+
+  // route IRQ to this CPU
+  Irq_mgr::mgr->set_cpu(irq(), cpu_id);
+}
+
+IMPLEMENT inline NEEDS["config.h", "kip.h"]
+Unsigned64
+Timer::system_clock()
+{
+  if (Config::Scheduler_one_shot)
+    return 0;
+  else
+    return Kip::k()->clock;
+}
+
+PUBLIC static inline NEEDS["io.h"]
+void Timer::acknowledge()
+{
+  Mword stat = Io::read<Mword>(TINT_STAT);
+  Io::write<Mword>(stat & (0x1f | (0x20 << Proc::cpu_id())), TINT_STAT);
+}

kernel/fiasco/src/kern/arm/bsp/exynos5/uart-arm-exynos5.cpp

@@ -0,0 +1,16 @@
+IMPLEMENTATION [arm && exynos5]: // ------------------------------
+
+IMPLEMENT int Uart::irq() const { return 32 + 53; }
+
+IMPLEMENTATION: // --------------------------------------------------------
+
+#include "mem_layout.h"
+#include "uart_s3c2410.h"
+
+IMPLEMENT Address Uart::base() const { return Mem_layout::Uart_base; }
+
+IMPLEMENT L4::Uart *Uart::uart()
+{
+  static L4::Uart_s5pv210 uart;
+  return &uart;
+}

kernel/fiasco/src/kern/arm/bsp/exynos5/warn-exynos5.cpp

@@ -0,0 +1,5 @@
+INTERFACE [exynos5]:
+#include "panic.h"
+
+#define NOT_IMPL WARN "%s not implemented", __PRETTY_FUNCTION__
+#define NOT_IMPL_PANIC panic("%s not implemented (from %p)\n", __PRETTY_FUNCTION__, __builtin_return_address((0)));

kernel/fiasco/src/kern/arm/bsp/imx/Kconfig

@@ -43,6 +43,13 @@ config PF_IMX_6
         help
           Choose for i.MX6 platform.
 
+config PF_IMX_53
+	bool "i.MX53"
+	depends on PF_IMX
+	select CAN_ARM_CPU_CORTEX_A8
+	help
+	  Choose for i.MX53
+
 endchoice
 
 config PF_IMX_RAM_PHYS_BASE
@@ -50,4 +57,5 @@ config PF_IMX_RAM_PHYS_BASE
 	default 0xc0000000 if PF_IMX_21
 	default 0x80000000 if PF_IMX_35
 	default 0x90000000 if PF_IMX_51
-        default 0x10000000 if PF_IMX_6
+	default 0x70000000 if PF_IMX_53
+	default 0x10000000 if PF_IMX_6

kernel/fiasco/src/kern/arm/bsp/imx/Modules

@@ -9,10 +9,12 @@ PREPROCESS_PARTS	+= $(if $(CONFIG_PF_IMX_51),imx51 imx_epit \
                                                     pic_gic pic_gic_mxc_tzic)
 PREPROCESS_PARTS	+= $(if $(CONFIG_PF_IMX_53),imx53 imx_epit \
                                                     pic_gic pic_gic_mxc_tzic)
+
 PREPROCESS_PARTS        += $(if $(CONFIG_PF_IMX_6),imx6 pic_gic mptimer)
 CONFIG_KERNEL_LOAD_ADDR := $(CONFIG_PF_IMX_RAM_PHYS_BASE)
 
 INTERFACES_KERNEL     += $(if $(CONFIG_PF_IMX_51),gic)
+INTERFACES_KERNEL     += $(if $(CONFIG_PF_IMX_53),gic)
 INTERFACES_KERNEL     += $(if $(CONFIG_PF_IMX_6),gic)
 MPCORE_PHYS_BASE      := 0x00a00000
 
@@ -24,6 +26,7 @@ pic_IMPL              += $(if $(CONFIG_PF_IMX_35),pic-arm-imx)
 pic_IMPL              += $(if $(CONFIG_PF_IMX_51),pic-gic pic-arm-imx51)
 pic_IMPL              += $(if $(CONFIG_PF_IMX_53),pic-gic pic-arm-imx51)
 pic_IMPL              += $(if $(CONFIG_PF_IMX_6),pic-gic pic-arm-imx51)
+
 bootstrap_IMPL        += bootstrap-arm-imx
 timer_IMPL            += $(if $(CONFIG_PF_IMX_21),timer-arm-imx21)
 timer_IMPL            += $(if $(CONFIG_PF_IMX_35),timer-arm-imx_epit)

kernel/fiasco/src/kern/arm/bsp/imx/mem_layout-arm-imx.cpp

@@ -118,3 +118,4 @@ public:
     Devices3_phys_base   = 0x02100000,
   };
 };
+

kernel/fiasco/src/kern/arm/cpu-arm.cpp

@@ -139,10 +139,19 @@ EXTENSION class Cpu
 {
 public:
   enum {
-    Cp15_c1_sw              = 1 << 10,
     Cp15_c1_ha              = 1 << 17,
-    Cp15_c1_ee              = 1 << 25,
     Cp15_c1_nmfi            = 1 << 27,
+  };
+};
+
+INTERFACE [arm && armv7 && (armca9 || armca15)]:
+
+EXTENSION class Cpu
+{
+public:
+  enum {
+    Cp15_c1_sw              = 1 << 10,
+    Cp15_c1_ee              = 1 << 25,
     Cp15_c1_te              = 1 << 30,
     Cp15_c1_rao_sbop        = (0xf << 3) | (1 << 16) | (1 << 18) | (1 << 22) | (1 << 23),
 
@@ -300,7 +309,44 @@ Cpu::early_init_platform()
 }
 
 //---------------------------------------------------------------------------
-IMPLEMENTATION [arm && !(mpcore || armca9)]:
+IMPLEMENTATION [arm && armca15]:
+PRIVATE static inline void
+Cpu::early_init_platform()
+{
+  Io::write<Mword>(Io::read<Mword>(Mem_layout::Gic_cpu_map_base + 0) | 1,
+                   Mem_layout::Gic_cpu_map_base + 0);
+  Io::write<Mword>(Io::read<Mword>(Mem_layout::Gic_dist_map_base + 0) | 1,
+                   Mem_layout::Gic_dist_map_base + 0);
+
+  Mem_unit::clean_dcache();
+
+  enable_smp();
+}
+
+//---------------------------------------------------------------------------
+IMPLEMENTATION [arm && mp && (mpcore || armca9)]:
+
+PUBLIC static inline NEEDS["mem_layout.h", "io.h"]
+int
+Cpu::num_cpus()
+{
+  return (Io::read<Mword>(Mem_layout::Mp_scu_map_base + 4) & 3) + 1;
+}
+
+
+//---------------------------------------------------------------------------
+IMPLEMENTATION [arm && mp && armca15]:
+
+PUBLIC static inline int
+Cpu::num_cpus()
+{
+  unsigned num;
+  asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r"(num));
+  return ((num >> 24) & 0x3)+ 1;
+}
+
+//---------------------------------------------------------------------------
+IMPLEMENTATION [arm && !(mpcore || armca9 || armca15)]:
 
 PRIVATE static inline void Cpu::early_init_platform()
 {}
@@ -501,13 +547,13 @@ Cpu::id_init()
 }
 
 //---------------------------------------------------------------------------
-IMPLEMENTATION [!arm_cpu_errata || !armv6plus]:
+IMPLEMENTATION [!arm_cpu_errata || !armv6plus || omap4_pandaboard]:
 
 PRIVATE static inline
 void Cpu::init_errata_workarounds() {}
 
 //---------------------------------------------------------------------------
-IMPLEMENTATION [arm_cpu_errata && armv6plus]:
+IMPLEMENTATION [arm_cpu_errata && armv6plus && !omap4_pandaboard]:
 
 PRIVATE static inline
 void
@@ -562,8 +608,8 @@ Cpu::init_errata_workarounds()
           if (rev == 0x20 || rev == 0x21 || rev == 0x22)
             set_c15_c0_1((1 << 12) | (1 << 22));
 
-          // errata: 743622
-          if ((rev & 0xf0) == 0x20)
+          // errata: 743622 (r2p0 - r2p2)
+          if ((rev & 0xf0) == 0x20 && (rev & 0xf) < 0x3)
             set_c15_c0_1(1 << 6);
 
           // errata: 751472

kernel/fiasco/src/kern/arm/fpu-arm.cpp

@@ -78,6 +78,7 @@ Fpu::copro_enable()
                "mcr  p15, 0, %0, c1, c0, 2\n"
                : : "r" (0), "I" (0x00f00000));
   Mem::dsb();
+  Mem::isb();
 }
 
 // ------------------------------------------------------------------------

kernel/fiasco/src/kern/arm/kernel_thread-arm.cpp

@@ -45,9 +45,9 @@ Kernel_thread::boot_app_cpus()
   extern volatile Mword _tramp_mp_startup_pdbr;
   extern volatile Mword _tramp_mp_start_dcr;
 
-  unsigned num_ap_cpus = (Io::read<Mword>(Mem_layout::Mp_scu_map_base + 4) & 3);
+  unsigned num_ap_cpus = Cpu::num_cpus();
 
-  printf("Number of CPUs: %d\n", num_ap_cpus + 1);
+  printf("Number of CPUs: %d\n", num_ap_cpus);
 
   _tramp_mp_startup_cp15_c1 = Config::Cache_enabled
                               ? Cpu::Cp15_c1_cache_enabled : Cpu::Cp15_c1_cache_disabled;

kernel/fiasco/src/kern/arm/mem_space-arm.cpp

@@ -477,7 +477,7 @@ Mem_space::next_asid(unsigned cpu)
 }
 
 //----------------------------------------------------------------------------
-IMPLEMENTATION [armv7 && armca9]:
+IMPLEMENTATION [armv7 && (armca9 || armca15)]:
 
 PRIVATE inline static
 unsigned long

kernel/fiasco/src/kern/arm/pagetable-arch.cpp

@@ -42,7 +42,7 @@ public:
 };
 
 //---------------------------------------------------------------------------
-INTERFACE[arm && !(mpcore || armca9)]:
+INTERFACE[arm && !(mpcore || armca9 || armca15)]:
 
 EXTENSION class Mem_page_attr
 {
@@ -59,7 +59,7 @@ public:
 };
 
 //---------------------------------------------------------------------------
-INTERFACE[arm && (mpcore || armca9)]:
+INTERFACE[arm && (mpcore || armca9 || armca15)]:
 
 EXTENSION class Mem_page_attr
 {
@@ -78,7 +78,7 @@ public:
 };
 
 //---------------------------------------------------------------------------
-INTERFACE[arm && armca9]:
+INTERFACE[arm && (armca9 || armca15)]:
 
 EXTENSION class Page_table
 {
@@ -477,7 +477,7 @@ void Page_table::activate(unsigned long asid)
 }
 
 //-----------------------------------------------------------------------------
-IMPLEMENTATION [armv7 && armca9]:
+IMPLEMENTATION [armv7 && (armca9 || armca15)]:
 
 PUBLIC
 void Page_table::activate(unsigned long asid)

kernel/fiasco/src/kern/arm/perf_cnt-arm.cpp

@@ -11,7 +11,7 @@ public:
 };
 
 // ------------------------------------------------------------------------
-INTERFACE [arm && perf_cnt && !(mpcore || armca8 || armca9)]:
+INTERFACE [arm && perf_cnt && !(mpcore || armca8 || armca9 || armca15)]:
 
 EXTENSION class Perf_cnt
 {
@@ -81,7 +81,7 @@ private:
 };
 
 // ------------------------------------------------------------------------
-INTERFACE [arm && perf_cnt && (armca8 || armca9)]:
+INTERFACE [arm && perf_cnt && (armca8 || armca9 || armca15)]:
 
 EXTENSION class Perf_cnt
 {
@@ -184,7 +184,7 @@ private:
 };
 
 // ------------------------------------------------------------------------
-INTERFACE [arm && perf_cnt && armca9]:
+INTERFACE [arm && perf_cnt && (armca9 || armca15)]:
 
 EXTENSION class Perf_cnt
 {
@@ -199,7 +199,7 @@ private:
 IMPLEMENTATION [arm && perf_cnt]:
 
 // ------------------------------------------------------------------------
-IMPLEMENTATION [arm && perf_cnt && !(mpcore || armca8 || armca9)]:
+IMPLEMENTATION [arm && perf_cnt && !(mpcore || armca8 || armca9 || armca15)]:
 
 char const *Perf_cnt::perf_type_str = "none";
 
@@ -284,7 +284,7 @@ Perf_cnt::mon_event_type(int nr)
 { return Io::read<unsigned char>(mon_event_type_addr(nr)); }
 
 // ------------------------------------------------------------------------
-IMPLEMENTATION [arm && perf_cnt && (armca8 || armca9)]:
+IMPLEMENTATION [arm && perf_cnt && (armca8 || armca9 || armca15)]:
 
 #include "cpu.h"
 

kernel/fiasco/src/kern/arm/startup-arm.cpp

@@ -65,4 +65,5 @@ Startup::stage2()
   Timer::init(0);
   Kern_lib_page::init();
   Utcb_init::init();
+  puts("Startup::stage2 finished");
 }

kernel/fiasco/src/kern/arm/thread-arm.cpp

@@ -315,6 +315,10 @@ extern "C" {
             if (handle_copro_fault[copro](opcode, ts))
               return;
           }
+
+        /* check for ARM default GDB breakpoint */
+        if (!(ts->psr & Proc::Status_thumb) && opcode == 0xe7ffdefe)
+          ts->pc -= 4;
       }
 
 undef_insn:
@@ -414,7 +418,7 @@ Thread::user_ip() const
 IMPLEMENT inline
 Mword
 Thread::user_flags() const
-{ return 0; }
+{ return state() & Thread_ready; }
 
 IMPLEMENT inline NEEDS[Thread::exception_triggered]
 void
@@ -613,6 +617,10 @@ Thread::condition_valid(Unsigned32 insn, Unsigned32 psr)
   return (v[insn >> 28] >> (psr >> 28)) & 1;
 }
 
+IMPLEMENT inline
+void Thread::user_single_step(bool)
+{}
+
 // ------------------------------------------------------------------------
 IMPLEMENTATION [arm && armv6plus]:
 

kernel/fiasco/src/kern/arm/tramp-mp.S

@@ -5,35 +5,56 @@
 	.p2align 12
 
 #ifdef CONFIG_ARM_V7
-/* See cache_func_gen.cpp */
-	.global v7_invalidate_l1
-invalidate_l1_v7:
+	/* Directly taken from the ARMV7 manual section 'Performing cache
+	   maintenance operations' */
+	.global v7_invalidate_dcache
+v7_invalidate_dcache:
+	mrc p15, 1, r0, c0, c0, 1  @Read CLIDR into R0
+	ands r3, r0, #0x07000000
+	mov r3, r3, lsr #23        @ Cache level value (naturally aligned)
+	beq finished
+	mov r10, #0
+loop1:
+	add r2, r10, r10, lsr #1    @ Work out 3 x cachelevel
+	mov r1, r0, lsr r2          @ bottom 3 bits are the Cache type for this level
+	and r1, r1, #7              @ get those 3 bits alone
+	cmp r1, #2
+	blt skip                    @ no cache or only instruction cache at this level
+	mcr p15, 2, r10, c0, c0, 0  @ write csselr from r10
+	isb                         @ ISB to sync the change to the CCSIDR
+	mrc p15, 1, r1, c0, c0, 0   @ read current CCSIDR to R1
+	
+	and r2, r1, #7              @ extract the line length field
+	add r2, r2, #4              @ add 4 for the line length offset (log2 16 bytes)
+	ldr r4, =0x3ff
+	ands r4, r4, r1, lsr #3     @ R4 is the max number on the way size (right aligned)
+	clz r5, r4                  @ R5 is the bit position of the way size increment
+	mov r9, r4                  @ R9 working copy of the max way size (right aligned)
+loop2:
+	ldr r7, =0x00007fff
+	ands r7, r7, r1, lsr #13    @ R7 is the max number of the index size (right aligned)
+loop3:
+	orr r11, r10, r9, lsl r5    @ factor in the way number and cache number into R11
+	orr r11, r11, r7, lsl r2    @ factor in the index number
+	mcr p15, 0, r11, c7, c14, 2 @ dccsw, clean/invalidate by set/way
+	subs r7, r7, #1             @ decrement the index
+	bge loop3
+
+	subs r9, r9, #1             @ decrement the way number
+	bge loop2
+
+skip:
+	add r10, r10, #2            @ increment the cache number
+	cmp r3, r10
+	bgt loop1
+
 	mov     r3, #0
 	mcr     p15, 2, r3, c0, c0, 0
-	mrc     p15, 1, r2, c0, c0, 0
-	mov     r3, r2, lsr #3
-	mov     r0, r2, lsr #13
-	mov     r3, r3, asl #22
-	mov     r3, r3, lsr #22
-	and     r2, r2, #7
-	mov     r0, r0, asl #17
-	add     ip, r2, #4
-	mov     r0, r0, lsr #17
-	mov     r2, r3
-	clz     r3, r3
-.L3:
-	mov     r4, r2, asl r3
-	mov     r1, r0
-.L2:
-	orr     r5, r4, r1, asl ip
-	mcr     p15, 0, r5, c7, c6, 2
-	subs    r1, r1, #1
-	bcs     .L2
-	subs    r2, r2, #1
-	bcs     .L3
-	isb
+
 	dsb
-	mov     pc, lr
+	isb
+finished:
+	mov pc, lr
 #endif
 
 	.global _tramp_mp_entry
@@ -44,14 +65,16 @@ _tramp_mp_entry:
 	msr   cpsr_c, r0
 
 	// enable SMP
+#ifndef CONFIG_ARM_CORTEX_A15
 	adr   r0, .Lmpcore_phys_base
 	ldr   r0, [r0]
 	ldr   r1, [r0]
 	orr   r1, #1
 	str   r1, [r0]
+#endif
 
 #ifdef CONFIG_ARM_V7
-	bl    invalidate_l1_v7
+	bl    v7_invalidate_dcache
 #endif
 
 	mcr   p15, 0, r0, c7, c5, 0 // ICIALLU
@@ -65,7 +88,7 @@ _tramp_mp_entry:
 #ifdef CONFIG_ARM_V7
 	// ACTRL is implementation defined
 	mrc   p15, 0, r0, c0, c0, 0  // read MIDR
-	adr   r3, .Lactrl_cpuid_a9   // load addr
+	adr   r3, .Lactrl_cpuid      // load addr
 	ldm   r3, {r1,r2}            // load mask + val
 	and   r0, r1                 // apply mask
 	teq   r0, r2                 // check value
@@ -73,9 +96,11 @@ _tramp_mp_entry:
 #endif
 
 	mrc   p15, 0, r0, c1, c0, 1
-#ifdef CONFIG_ARM_V7
-        tst   r0, #0x40
-        bne   2f
+#ifdef CONFIG_ARM_CORTEX_A15
+	orr  r0, r0, #0x40
+#elif defined CONFIG_ARM_V7
+	tst   r0, #0x40
+	bne   2f
 	orr   r0, r0, #0x41
 #else
 	orr   r0, r0, #0x20
@@ -114,10 +139,20 @@ _tramp_mp_entry:
 .Lmpcore_phys_base:
 	.long MPCORE_PHYS_BASE
 
-// only one currently
-.Lactrl_cpuid_a9:
+#ifdef CONFIG_ARM_CORTEX_A9
+.Lactrl_cpuid:
          .long 0xff0ffff0
          .long 0x410fc090
+#elif defined CONFIG_ARM_CORTEX_A15
+.Lactrl_cpuid:
+         .long 0xff0ffff0
+         .long 0x410fc0f0
+#else
+.Lactrl_cpuid:
+         .long 0xffffffff
+         .long 0x0
+#endif
+
 
 	// we run paged now
 _tramp_mp_virt:

kernel/fiasco/src/kern/ia32/32/entry-native.S

@@ -46,6 +46,30 @@
 	jmp	slowtraps
 .endm
 
+#ifdef CONFIG_USER_SINGLE_STEP
+.macro HANDLE_USER_TRAP1
+	/* Save EFLAGS, this may trap if user task had single stepping activated
+	 * test for single stepping
+	 */
+	pushf
+	addl	$4, %esp
+	testl	$EFLAGS_TF, -4(%esp)
+.endm
+
+.macro RESTORE_USER_TRAP1
+	/* Restore single stepping if it has been set */
+	je 1f
+	orl $EFLAGS_TF, (%esp)
+1:
+.endm
+#else
+.macro HANDLE_USER_TRAP1
+.endm
+
+.macro RESTORE_USER_TRAP1
+.endm
+#endif
+
 	.p2align 4
 	.globl	entry_vec01_debug
 entry_vec01_debug:
@@ -59,6 +83,15 @@ entry_vec01_debug:
 	cmpl	$entry_sys_fast_ipc_log, (%esp)
 	je	2f
 #endif
+
+	/* test if trap was raised within kernel */
+	testl $3, 4(%esp)
+	jne   1f
+
+	/* turn of EFLAGS.TF */
+	btrl $7, 8(%esp) 
+	iret
+
 1:	pushl	$0
 	pushl	$1
 	pusha
@@ -226,10 +259,16 @@ alien_sys_fast_ipc_log:
 	.p2align(4)
 	.global entry_sys_fast_ipc_c
 entry_sys_fast_ipc_c:
+
+	HANDLE_USER_TRAP1
+
 	pop	%esp
 	pushl	$(GDT_DATA_USER|SEL_PL_U)	/* user ss */
 	pushl	%ebp				// push user SP (get in ebp)
 	pushf                                   // fake user eflags
+
+	RESTORE_USER_TRAP1
+
 	cld
 	// Fake user cs. This cs value is never used with exception
 	// that the thread is ex_regs'd before we leave with sysexit.

kernel/fiasco/src/kern/ia32/config-ia32.cpp

@@ -86,6 +86,12 @@ public:
 //  static const bool hlt_works_ok = false;
   static bool hlt_works_ok;
 
+#ifdef CONFIG_USER_SINGLE_STEP
+  static const bool user_single_step = true;
+#else
+  static const bool user_single_step = false;
+#endif
+
   // the default uart to use for serial console
   static const unsigned default_console_uart = 1;
   static const unsigned default_console_uart_baudrate = 115200;

kernel/fiasco/src/kern/ia32/thread-ia32.cpp

@@ -92,7 +92,7 @@ Thread::user_ip() const
 IMPLEMENT inline
 Mword
 Thread::user_flags() const
-{ return regs()->flags(); }
+{ return state() & Thread_ready; }
 
 /** Check if the pagefault occured at a special place: At some places in the
     kernel we want to ensure that a specific address is mapped. The regular
@@ -188,6 +188,10 @@ Thread::handle_slow_trap(Trap_state *ts)
       goto generic_debug;
     }
 
+  if (Config::user_single_step && ts->_trapno == 1 && from_user)
+    if (send_exception(ts))
+      goto success;
+
   if (from_user && _space.user_mode())
     {
       if (ts->_trapno == 14 && Kmem::is_io_bitmap_page_fault(ts->_cr2))
@@ -435,7 +439,8 @@ Thread::send_exception_arch(Trap_state *ts)
   // thread (not alien) and it's a debug trap,
   // debug traps for aliens are always reflected as exception IPCs
   if (!(state() & Thread_alien)
-      && (ts->_trapno == 1 || ts->_trapno == 3))
+      && ((ts->_trapno == 1 && !Config::user_single_step)
+      ||   ts->_trapno == 3))
     return 0; // we do not handle this
 
   if (ts->_trapno == 3)
@@ -488,6 +493,11 @@ Thread::user_ip(Mword ip)
     }
 }
 
+IMPLEMENT inline
+void
+Thread::user_single_step(bool)
+{}
+
 //----------------------------------------------------------------------------
 IMPLEMENTATION [(ia32,amd64,ux) && !io]:
 
@@ -840,3 +850,16 @@ PRIVATE static inline
 int
 Thread::call_nested_trap_handler(Trap_state *)
 { return -1; }
+
+//---------------------------------------------------------------------------
+IMPLEMENTATION [ia32]:
+
+IMPLEMENT inline
+void
+Thread::user_single_step(bool enable)
+{
+  if (!Config::user_single_step)
+    return;
+
+  regs()->flags(enable ? user_flags() | EFLAGS_TF : user_flags() & ~EFLAGS_TF);
+}

kernel/fiasco/src/kern/irq_mgr.cpp

@@ -124,5 +124,9 @@ IMPLEMENT
 void
 Irq_mgr::set_cpu(Mword irqnum, unsigned cpu) const
 {
-  WARNX(Warning, "IRQ%ld: ignoring CPU setting (%d).\n", irqnum, cpu);
+  Irq i = chip(irqnum);
+  if (!i.chip)
+    return;
+
+  i.chip->set_cpu(i.pin, cpu);
 }

kernel/fiasco/src/kern/ppc32/thread-ppc32.cpp

@@ -308,6 +308,10 @@ Thread::user_ip(Mword ip)
     }
 }
 
+IMPLEMENT inline
+void Thread::user_single_step(bool)
+{}
+
 PUBLIC inline NEEDS ["trap_state.h"]
 int
 Thread::send_exception_arch(Trap_state * /*ts*/)

kernel/fiasco/src/kern/task.cpp

@@ -484,10 +484,12 @@ Task::sys_caps_equal(Syscall_frame *, Utcb *utcb)
   if (obj_a.special() || obj_b.special())
     return commit_result(obj_a.special_cap() == obj_b.special_cap());
 
-  Obj_space::Capability c_a = lookup(obj_a.cap());
-  Obj_space::Capability c_b = lookup(obj_b.cap());
+  Kobject_iface* ki_a = lookup(obj_a.cap()).obj();
+  Kobject_iface* ki_b = lookup(obj_b.cap()).obj();
+  Address a_a = ki_a ? ki_a->kobject_start_addr() : 0;
+  Address a_b = ki_b ? ki_b->kobject_start_addr() : 0;
 
-  return commit_result(c_a == c_b);
+  return commit_result(a_a == a_b);
 }
 
 PRIVATE inline NOEXPORT

kernel/fiasco/src/kern/thread.cpp

@@ -73,6 +73,7 @@ public:
   {
     Exr_cancel            = 0x10000,
     Exr_trigger_exception = 0x20000,
+    Exr_single_step       = 0x40000,
   };
 
   enum Vcpu_ctl_flags
@@ -140,6 +141,8 @@ public:
 
   inline Mword user_flags() const;
 
+  inline void user_single_step(bool);
+
   /** nesting level in debugger (always critical) if >1 */
   static Per_cpu<unsigned long> nested_trap_recover;
   static void handle_remote_requests_irq() asm ("handle_remote_cpu_requests");

kernel/fiasco/src/kern/thread_object.cpp

@@ -527,6 +527,8 @@ Thread_object::ex_regs(Address ip, Address sp,
   if (o_ip) *o_ip = user_ip();
   if (o_flags) *o_flags = user_flags();
 
+  (ops & Exr_single_step) ? user_single_step(true) : user_single_step(false);
+
   // Changing the run state is only possible when the thread is not in
   // an exception.
   if (!(ops & Exr_cancel) && (state() & Thread_in_exception))

kernel/fiasco/src/kern/timer_tick-multi-vector.cpp

@@ -0,0 +1,55 @@
+INTERFACE:
+
+#include "types.h"
+#include "per_cpu_data.h"
+
+EXTENSION class Timer_tick
+{
+public:
+  static Per_cpu<Timer_tick> _glbl_timer;
+
+  Timer_tick()
+  {
+   if (Proc::cpu_id())
+     set_hit(&handler_app);
+   else
+     set_hit(&handler_sys_time);
+  }
+};
+
+IMPLEMENTATION:
+
+#include "timer.h"
+
+DEFINE_PER_CPU Per_cpu<Timer_tick> Timer_tick::_glbl_timer;
+
+IMPLEMENT void
+Timer_tick::setup(unsigned cpu)
+{
+  if (!allocate_irq(&_glbl_timer.cpu(cpu), Timer::irq()))
+    panic("Could not allocate scheduling IRQ %d\n", Timer::irq());
+
+  _glbl_timer.cpu(cpu).set_mode(Timer::irq_mode());
+}
+
+IMPLEMENT
+void
+Timer_tick::enable(unsigned)
+{
+  _glbl_timer.current().chip()->unmask(_glbl_timer.current().pin());
+}
+
+IMPLEMENT
+void
+Timer_tick::disable(unsigned)
+{
+  _glbl_timer.current().chip()->mask(_glbl_timer.current().pin());
+}
+
+PUBLIC inline NEEDS["timer.h"]
+void
+Timer_tick::ack()
+{
+  Timer::acknowledge();
+  Irq_base::ack();
+}

l4/mk/platforms/arndale.conf

@@ -0,0 +1,4 @@
+PLATFORM_NAME        = "Arndale Board"
+PLATFORM_ARCH        = arm
+PLATFORM_RAM_BASE    = 0x40000000
+PLATFORM_RAM_SIZE_MB = 2048

l4/mk/platforms/imx53.conf

@@ -0,0 +1,4 @@
+PLATFORM_NAME        = "Freescale i.MX53"
+PLATFORM_ARCH        = arm
+PLATFORM_RAM_BASE    = 0x70000000
+PLATFORM_RAM_SIZE_MB = 1024

l4/pkg/bootstrap/server/src/Make.rules

@@ -80,8 +80,10 @@ SUPPORT_CC_arm-tegra2      := platform/tegra2.cc
 SUPPORT_CC_arm-imx21       := platform/imx.cc
 SUPPORT_CC_arm-imx35       := platform/imx.cc
 SUPPORT_CC_arm-imx51       := platform/imx.cc
+SUPPORT_CC_arm-imx53       := platform/imx.cc
 SUPPORT_CC_arm-imx6        := platform/imx.cc
 SUPPORT_CC_arm-om          := platform/om.cc
+SUPPORT_CC_arm-arndale     := platform/arndale.cc
 SUPPORT_CC_arm-kirkwood    := platform/kirkwood.cc
 DEFAULT_RELOC_arm-imx21    := 0x00200000  # because of blob
 

l4/pkg/bootstrap/server/src/platform/arndale.cc

@@ -0,0 +1,32 @@
+/**
+ * \file   arnadale.cc
+ * \brief  Support for the OpenMoko platform
+ *
+ * \date   2012
+ * \author Genode Labs
+ *
+ */
+
+
+#include "support.h"
+
+#include <l4/drivers/uart_s3c2410.h>
+#include <l4/drivers/uart_dummy.h>
+
+namespace {
+class Platform_arm_arndale : public Platform_single_region_ram
+{
+  bool probe() { return true; }
+
+  void init()
+  {
+    static L4::Uart_s5pv210 _uart;
+    static L4::Io_register_block_mmio r(0x12C20000);
+
+    _uart.startup(&r);
+    set_stdio_uart(&_uart);
+  }
+};
+}
+
+REGISTER_PLATFORM(Platform_arm_arndale);

l4/pkg/bootstrap/server/src/platform/imx.cc

@@ -36,6 +36,9 @@ class Platform_arm_imx : public Platform_single_region_ram
 #elif defined(PLATFORM_TYPE_imx51)
     static L4::Io_register_block_mmio r(0x73fbc000);
     static L4::Uart_imx51 _uart;
+#elif defined(PLATFORM_TYPE_imx53)
+    static L4::Io_register_block_mmio r(0x53fbc000);
+    static L4::Uart_imx51 _uart;
 #elif defined(PLATFORM_TYPE_imx6)
     //static L4::Io_register_block_mmio r(0x02020000); // UART1
     static L4::Io_register_block_mmio r(0x021e8000); // UART2

l4/pkg/sigma0/server/src/init.cc

@@ -27,6 +27,7 @@
 #include "ioports.h"
 #include "mem_man_test.h"
 #include <l4/sys/debugger.h>
+#include <l4/sys/scheduler.h>
 
 /* started as the L4 sigma0 task from crt0.S */
 
@@ -61,6 +62,10 @@ init(l4_kernel_info_t *info)
   l4_debugger_set_object_name(L4_BASE_FACTORY_CAP, "root factory");
   l4_debugger_set_object_name(L4_BASE_THREAD_CAP,  "sigma0");
 
+  l4_sched_param_t params = l4_sched_param(255);
+  l4_scheduler_run_thread(L4_BASE_SCHEDULER_CAP, L4_BASE_THREAD_CAP, &params);
+
+
   Page_alloc_base::init();
 
   init_memory(info);

l4/pkg/sigma0/server/src/ioports_x86.cc

@@ -39,8 +39,9 @@ void handle_io_page_fault(l4_umword_t t, l4_utcb_t *utcb, Answer *a)
   size = l4_fpage_size(fp) + PORT_SHIFT;
 
   unsigned long i = io_ports.alloc(Region::bs(port, 1UL << size, t));
-  if (i == port)
+  if (i == port) {
     a->snd_fpage(l4_iofpage(port >> PORT_SHIFT, size - PORT_SHIFT));
-  else
+    a->tag = l4_msgtag(0, 0, 1, 0);
+  } else
     a->error(L4_ENOMEM);
 }