alex/foc
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

FOC: Arndale bootstrapping

Browse Source 
Added 'exynos5' bsp, enabled MMU and UART, disabled caches.
This commit is contained in:
Sebastian Sumpf
2013-01-29 12:48:39 +01:00
parent 3ba6b97b55
commit 3044dc5c46
20 changed files with 238 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
kernel/fiasco/src/Kconfig
View File

@@ -114,6 +114,9 @@ config CAN_ARM_CPU_CORTEX_A8
config CAN_ARM_CPU_CORTEX_A9
bool
config CAN_ARM_CPU_CORTEX_A15
bool
config CAN_ARM_CACHE_L2CXX0
bool
@@ -161,6 +164,10 @@ config ARM_CORTEX_A9
bool "ARM Cortex-A9 CPU"
depends on CAN_ARM_CPU_CORTEX_A9
config ARM_CORTEX_A15
bool "ARM Cortex-A15 CPU"
depends on CAN_ARM_CPU_CORTEX_A15
config IA32_486
bool "Intel 80486"
depends on IA32
@@ -763,7 +770,7 @@ config ARM_V6
def_bool y if ARM_1136 || ARM_1176 || ARM_MPCORE
config ARM_V7
def_bool y if ARM_CORTEX_A8 || ARM_CORTEX_A9
def_bool y if ARM_CORTEX_A8 || ARM_CORTEX_A9 || ARM_CORTEX_A15
config ARM_V6PLUS
def_bool y if ARM_V6 || ARM_V7

1
kernel/fiasco/src/Modules.arm
View File

@@ -29,6 +29,7 @@ PREPROCESS_PARTS-$(CONFIG_ARM_1176) += arm1176
PREPROCESS_PARTS-$(CONFIG_ARM_MPCORE) += mpcore
PREPROCESS_PARTS-$(CONFIG_ARM_CORTEX_A8) += armca8
PREPROCESS_PARTS-$(CONFIG_ARM_CORTEX_A9) += armca9
PREPROCESS_PARTS-$(CONFIG_ARM_CORTEX_A15) += armca15
PREPROCESS_PARTS-$(CONFIG_ARM_TZ) += tz
PREPROCESS_PARTS-$(CONFIG_ARM_1176_CACHE_ALIAS_FIX) += arm1176_cache_alias_fix
PREPROCESS_PARTS-$(CONFIG_ARM_CPU_ERRATA) += arm_cpu_errata

8
kernel/fiasco/src/drivers/arm/mmu-arm.cpp
View File

@@ -171,7 +171,7 @@ FIASCO_NOINLINE void Mmu<Flush_area, Ram>::inv_dcache(void const *start, void co
}
//-----------------------------------------------------------------------------
IMPLEMENTATION [arm && (mpcore || arm1136 || arm1176 || armca8 || armca9)]:
IMPLEMENTATION [arm && (mpcore || arm1136 || arm1176 || armca8 || armca9 || armca15)]:
IMPLEMENT inline
template< unsigned long Flush_area, bool Ram >
@@ -303,7 +303,7 @@ void Mmu<Flush_area, Ram>::flush_dcache()
//-----------------------------------------------------------------------------
INTERFACE [arm && (armca8 || armca9)]:
INTERFACE [arm && (armca8 || armca9 || armca15)]:
EXTENSION class Mmu
{
@@ -344,7 +344,7 @@ EXTENSION class Mmu
};
//-----------------------------------------------------------------------------
INTERFACE [arm && armca9]:
INTERFACE [arm && (armca9 || armca15)]:
EXTENSION class Mmu
{
@@ -362,7 +362,7 @@ EXTENSION class Mmu
};
//-----------------------------------------
IMPLEMENTATION [arm && (armca8 || armca9)]:
IMPLEMENTATION [arm && (armca8 || armca9 || armca15)]:
PRIVATE
template< unsigned long Flush_area, bool Ram >

2
kernel/fiasco/src/drivers/arm/processor-arm.cpp
View File

@@ -222,7 +222,7 @@ void Proc::halt()
}
//----------------------------------------------------------------
IMPLEMENTATION[arm && (armca8 || armca9)]:
IMPLEMENTATION[arm && (armca8 || armca9 || armca15)]:
IMPLEMENT static inline
void Proc::pause()

15
kernel/fiasco/src/kern/arm/bootstrap.cpp
View File

@@ -80,6 +80,19 @@ IMPLEMENTATION [arm && !arm1176_cache_alias_fix]:
static void do_arm_1176_cache_alias_workaround() {}
//---------------------------------------------------------------------------
IMPLEMENTATION [arm && exynos5_arndale]:
static inline void supervisor_mode()
{
asm volatile ("cps #19");
}
//---------------------------------------------------------------------------
IMPLEMENTATION [arm && !exynos5_arndale]:
static inline void supervisor_mode() { }
//---------------------------------------------------------------------------
IMPLEMENTATION [arm]:
@@ -145,6 +158,8 @@ extern "C" void bootstrap_main()
extern char kernel_page_directory[];
void *const page_dir = kernel_page_directory + Virt_ofs;
supervisor_mode();
Address va, pa;
// map sdram linear from 0xf0000000
for (va = Mem_layout::Map_base, pa = Mem_layout::Sdram_phys_base;

15
kernel/fiasco/src/kern/arm/bsp/exynos5/Kconfig Normal file
View File

@@ -0,0 +1,15 @@
# PF: EXYNOS5
# PFDESCR: Samsung Exynos5
# PFDEPENDS: ARM
choice
prompt "Exynos5 Platform"
default PF_EXYNOS5_ARNDALE
config PF_EXYNOS5_ARNDALE
bool "Samsung Arndale"
depends on PF_EXYNOS5
select CAN_ARM_CPU_CORTEX_A15
help
Choose for Arndale board platform.
endchoice

20
kernel/fiasco/src/kern/arm/bsp/exynos5/Modules Normal file
View File

@@ -0,0 +1,20 @@
# vim:set ft=make:
SUBSYSTEMS += LIBUART
OBJECTS_LIBUART += uart_s3c2410.o
PREPROCESS_PARTS += exynos5 libuart
PREPROCESS_PARTS += $(if $(CONFIG_PF_EXYNOS5_ARNDALE), exynos5_arndale)
CONFIG_KERNEL_LOAD_ADDR := 0x40000000
bootstrap_IMPL += bootstrap-arm-exynos5
clock_IMPL += clock-generic
config_IMPL += config-arm-exynos5
kernel_uart_IMPL += kernel_uart-arm-exynos5
mem_layout_IMPL += mem_layout-arm-exynos5
pic_IMPL += pic-arm-gic-exynos5
reset_IMPL += reset-arm-exynos5
timer_IMPL += timer-arm-exynos5
timer_tick_IMPL += timer_tick-single-vector
uart_IMPL += uart-arm-exynos5
warn_IMPL += warn warn-exynos5

17
kernel/fiasco/src/kern/arm/bsp/exynos5/bootstrap-arm-exynos5.cpp Normal file
View File

@@ -0,0 +1,17 @@
INTERFACE [arm && exynos5]:
enum {
Cache_flush_area = 0,
};
IMPLEMENTATION [arm && exynos5]:
#include "mem_layout.h"
#include "io.h"
void
map_hw(void *pd)
{
map_dev<Mem_layout::Devices1_phys_base>(pd, 1);
map_dev<Mem_layout::Devices2_phys_base>(pd, 2);
}

3
kernel/fiasco/src/kern/arm/bsp/exynos5/config-arm-exynos5.cpp Normal file
View File

@@ -0,0 +1,3 @@
INTERFACE[arm && exynos5_arndale]: //-----------------------------------------
#define TARGET_NAME "ArndaleBoard"

12
kernel/fiasco/src/kern/arm/bsp/exynos5/kernel_uart-arm-exynos5.cpp Normal file
View File

@@ -0,0 +1,12 @@
INTERFACE:
// On ARM the MMIO for the uart is accessible before the MMU is fully up
EXTENSION class Kernel_uart { enum { Bsp_init_mode = Init_before_mmu }; };
IMPLEMENTATION [arm && exynos5 && serial]:
IMPLEMENT
bool Kernel_uart::startup(unsigned, int)
{
return Uart::startup();
}

26
kernel/fiasco/src/kern/arm/bsp/exynos5/mem_layout-arm-exynos5.cpp Normal file
View File

@@ -0,0 +1,26 @@
INTERFACE [arm && exynos5]:
EXTENSION class Mem_layout
{
public:
enum Phys_layout_exynos5 : Address {
Devices1_phys_base = 0x10000000,
Devices2_phys_base = 0x12c00000,
};
enum Virt_layout_exynos5 : Address {
Uart2_map_base = Devices2_map_base + 0x20000,
};
};
INTERFACE [arm && exynos5_arndale]:
EXTENSION class Mem_layout
{
public:
enum Virt_layout_exynos5_arndale : Address {
Uart_base = Uart2_map_base,
Sdram_phys_base = 0x40000000,
};
};

26
kernel/fiasco/src/kern/arm/bsp/exynos5/pic-arm-gic-exynos5.cpp Normal file
View File

@@ -0,0 +1,26 @@
IMPLEMENTATION [arm && exynos5]:
#include "panic.h"
#include "warn.h"
#include "initcalls.h"
IMPLEMENT FIASCO_INIT
void
Pic::init()
{
NOT_IMPL_PANIC;
}
IMPLEMENT inline
Pic::Status Pic::disable_all_save()
{ return 0; }
IMPLEMENT inline
void Pic::restore_all(Status)
{}
extern "C"
void irq_handler()
{
NOT_IMPL_PANIC;
}

15
kernel/fiasco/src/kern/arm/bsp/exynos5/reset-arm-exynos5.cpp Normal file
View File

@@ -0,0 +1,15 @@
IMPLEMENTATION [arm && exynos5]:
#include "io.h"
#include "kmem.h"
void __attribute__ ((noreturn))
platform_reset(void)
{
enum { PRM_RSTCTRL = Kmem::Devices1_map_base + 0x40400 };
Io::write<Mword>(1, PRM_RSTCTRL);
for (;;)
;
}

39
kernel/fiasco/src/kern/arm/bsp/exynos5/timer-arm-exynos5.cpp Normal file
View File

@@ -0,0 +1,39 @@
INTERFACE [arm & exynos5]:
EXTENSION class Timer
{
public:
static unsigned irq() { return 64; /* timer0 */ }
};
IMPLEMENTATION [arm && exynos5]:
#include "warn.h"
IMPLEMENT inline
void
Timer::update_one_shot(Unsigned64 wakeup)
{
(void)wakeup;
}
IMPLEMENT
void Timer::init(unsigned)
{
// NOT_IMPL_PANIC;
}
IMPLEMENT inline NEEDS["warn.h"]
Unsigned64
Timer::system_clock()
{
NOT_IMPL_PANIC;
return 0;
}
PUBLIC static inline NEEDS["warn.h"]
void Timer::acknowledge()
{
NOT_IMPL_PANIC;
}

16
kernel/fiasco/src/kern/arm/bsp/exynos5/uart-arm-exynos5.cpp Normal file
View File

@@ -0,0 +1,16 @@
IMPLEMENTATION [arm && exynos5]: // ------------------------------
IMPLEMENT int Uart::irq() const { return 32 + 54; }
IMPLEMENTATION: // --------------------------------------------------------
#include "mem_layout.h"
#include "uart_s3c2410.h"
IMPLEMENT Address Uart::base() const { return Mem_layout::Uart_base; }
IMPLEMENT L4::Uart *Uart::uart()
{
static L4::Uart_s5pv210 uart;
return &uart;
}

5
kernel/fiasco/src/kern/arm/bsp/exynos5/warn-exynos5.cpp Normal file
View File

@@ -0,0 +1,5 @@
INTERFACE [exynos5]:
#include "panic.h"
#define NOT_IMPL WARN "%s not implemented", __PRETTY_FUNCTION__
#define NOT_IMPL_PANIC panic("%s not implemented\n", __PRETTY_FUNCTION__);

2
kernel/fiasco/src/kern/arm/config-arm.cpp
View File

@@ -45,7 +45,7 @@ public:
enum
{
Cache_enabled = true,
Cache_enabled = false,
};
static const char char_micro;

15
kernel/fiasco/src/kern/arm/cpu-arm.cpp
View File

@@ -139,10 +139,19 @@ EXTENSION class Cpu
{
public:
enum {
Cp15_c1_sw = 1 << 10,
Cp15_c1_ha = 1 << 17,
Cp15_c1_ee = 1 << 25,
Cp15_c1_nmfi = 1 << 27,
};
};
INTERFACE [arm && armv7 && (armca9 || armca15)]:
EXTENSION class Cpu
{
public:
enum {
Cp15_c1_sw = 1 << 10,
Cp15_c1_ee = 1 << 25,
Cp15_c1_te = 1 << 30,
Cp15_c1_rao_sbop = (0xf << 3) | (1 << 16) | (1 << 18) | (1 << 22) | (1 << 23),
@@ -507,7 +516,7 @@ PRIVATE static inline
void Cpu::init_errata_workarounds() {}
//---------------------------------------------------------------------------
IMPLEMENTATION [arm_cpu_errata && armv6plus]:
IMPLEMENTATION [arm_cpu_errata && armv6plus && !omap4_pandaboard]:
PRIVATE static inline
void

2
kernel/fiasco/src/kern/arm/mem_space-arm.cpp
View File

@@ -477,7 +477,7 @@ Mem_space::next_asid(unsigned cpu)
}
//----------------------------------------------------------------------------
IMPLEMENTATION [armv7 && armca9]:
IMPLEMENTATION [armv7 && (armca9 || armca15)]:
PRIVATE inline static
unsigned long

2
kernel/fiasco/src/kern/arm/pagetable-arch.cpp
View File

@@ -477,7 +477,7 @@ void Page_table::activate(unsigned long asid)
}
//-----------------------------------------------------------------------------
IMPLEMENTATION [armv7 && armca9]:
IMPLEMENTATION [armv7 && (armca9 || armca15)]:
PUBLIC
void Page_table::activate(unsigned long asid)