28 Commits

Author SHA1 Message Date
Sebastian Sumpf
8fb47446ed foc: adjust panda timer to version A6
A6 runs at 800 not 700 MHz (as the ES2 does) when bootstrapped by U-boot

(thanks to mstein)
2017-03-08 16:58:27 +01:00
Christian Helmuth
4e0373fe5e Create tmp files in OBJ_DIR not L4_DIR
Fixes #15
2016-05-17 17:16:19 +02:00
Reinier Millo Sánchez
818a435e9e foc: handle IRQ in TrustZone's normal side with security extensions
Fix #13
2015-07-01 13:02:16 +02:00
Christian Prochaska
8469170306 Relocate sigma0 to a higher address
... to prevent an overlap with the kernel.

Fixes ssumpf/foc#11
2015-05-19 11:38:16 +02:00
Christian Prochaska
0644e90c5d Fixes for building with GCC 4.9
This commit can be removed when updating to the latest Fiasco.OC version.

Fixes ssumpf/foc#10
2015-05-11 17:24:12 +02:00
Alexander Boettcher
1acdeeb381 FOC: cli in context of leave_by_trigger_exception
Bug triggering on 64bit. Without the cli (as used on 32bit) the assertion
in kernel/fiasco/src/kern/thread-ipc.cpp:739 triggers.
2015-02-24 16:35:19 +01:00
Christian Prochaska
7cd187003d Flush the TLB after idle operation
While a CPU executes the idle thread, it receives no cross-CPU TLB flush
requests. Therefore, the TLB needs to get flushed when leaving the idle
thread to compensate for any missed flush requests.

Fixes ssumpf/foc#9.
2013-10-30 08:56:32 +01:00
Christian Prochaska
591c89a3ae limit the exception reply thread state application
Don't apply those parts of the thread state returned by the Genode
exception handler which might have changed in the kernel in
the meantime.

Fixes ssumpf/foc#8.
2013-10-25 16:00:10 +02:00
Stefan Kalkowski
90a76c9592 Enable performance counter for everything beyond Armv7 2013-08-28 20:46:17 +02:00
Sebastian Sumpf
14ef3a3a2b FOC: Don't set SCU enable bit on Cortex-A15
... since the SCU-control register does not exist (resverved area on Cortex-A15).
Setting this bit leads to second-level translation table faults on CPU1.
2013-08-13 12:34:55 +02:00
Sebastian Sumpf
82f255fff2 FOC/L4RE: Add license 2013-08-09 12:20:50 +02:00
Sebastian Sumpf
05001c3f3c FOC: Fix in kernel 'Op_cache_dma_coherent'
'Mem_unit::flush_dcache' takes void pointers as arguments, no need to take the
given void pointers ('start' and 'end') and transform them to
'Virt_addr(Address(x)' types. This breaks cache flushing in r56.
2013-08-08 14:48:45 +02:00
Sebastian Sumpf
4239a0e015 FOC: Rate OMAP4 timer at 350 MHz
Only valid for PandaBoard ES2 where u-boot sets the MPU clock to 700 MHz (of
possible 1200 MHz) only.
2013-07-18 10:53:16 +02:00
Sebastian Sumpf
3db87defce FOC: Make PandaBoard compile
Fix multiple definition of 'init_errata_workarounds'
2013-07-17 12:13:41 +02:00
Sebastian Sumpf
ff8fb8c677 L4RE: Remove <cstdio> from Exynos init code 2013-07-16 16:50:20 +02:00
Sebastian Sumpf
4df9ea5598 i.MX53 support
Was: 'imx53_support.patch'
2013-07-16 16:22:08 +02:00
Alexander Boettcher
d51aad39f1 Read out comport on x86 from BDA area
With this patch the comport are tried to read out from the BIOS Data Area
on x86 machines. The BDA Area are part of the first physical page and may
contain the non-default io ports of the comport.

When used together with 'bender' from the 'morbo' toolchain, even serial PCI
cards (also Intel's AMT Serial Over Line adapter) are detected automatically.
2013-07-16 12:23:15 +02:00
Christian Prochaska
6c831301d9 FOC: Fetch serial input without '-serial_esc' option
With this patch, the kernel fetches serial data also when the
'-serial_esc' option is not set.

To keep the patch minimally invasive, the 'serial ESC' functionality gets
enabled by default and the existence of the '-serial_esc' argument gets only
checked when an ESC character was received and the decision of entering the
kernel debugger or not needs to be made.

Fixes ssumpf/foc#3.
2013-07-16 12:23:15 +02:00
Christian Prochaska
fded832001 FOC: Disable the virtual console echo
This patch is needed for the Genode KDB terminal.

Fixes ssumpf/foc#1.
2013-07-16 12:23:15 +02:00
Sebastian Sumpf
300faf9de7 L4RE: Remove 'moe' from 'switch_ram_base' target 2013-07-16 12:23:15 +02:00
Sebastian Sumpf
ba7ccbdae7 Sigma0: raise sigma0's priority to maximum.
When sigma0 runs on a lower priority than the rest of the threads in the system
it might come to the point that while answering a page fault or I/O memory area
request the timeslice of the caller (core-pager) gets fully consumed. As long as
other threads are still executable and don't block sigma0 won't do progress
anymore, because it runs at the lowest priority.  This commit simply sets
sigma0's priority to the highest in the system.

Was: 'sigma0_prio.patch'
2013-07-16 12:23:14 +02:00
Sebastian Sumpf
ff7ce2a41a Fiasco.OC: fix io-port fault answer in sigma0
In sigma0 normally no answer tag to a request/fault is created. It
simply uses the message tag received with the request. This doesn't work out
when I/O ports are requested. This patch constructs an appropriate answer tag.
Moreover, we have to enable I/O port protection in the kernel configuration.

Was: 'sigma0_ioport.patch'
2013-07-16 12:23:14 +02:00
Sebastian Sumpf
127e1f9219 JBD: Increase name buffer to 32K
Increase the size of the JDB kernel object names buffer. The original size was
too small for some Genode scenarios and caused missing thread names in the
kernel debugger thread list.

Was: 'jdb_kobject_names.patch'
2013-07-16 12:23:14 +02:00
Sebastian Sumpf
8adcd665fb X86: Single stepping
This patch enables the user land to use the CPU's single stepping mode on
x86_32 platforms. It is needed to enable the use of GDB monitor for
user-level debugging.

Was: 'foc_single_step_x86.patch'
2013-07-16 12:23:14 +02:00
Sebastian Sumpf
eb39c103a6 Ex_regs: Change 'user_flags'
Return true if thread is ready.

Was: 'foc_exregs_ret_state.patch'
2013-07-16 12:23:13 +02:00
Sebastian Sumpf
d6ec37874b Caps: fix l4_task_cap_equal semantic.
The syscall l4_task_cap_equal almost returns false although the referenced
kernel-objects are equal. This patch changes the semantic of the syscall so that
whenever two capabilities refering the same kernel-object are compared it will
return true. Please refer to the discussion of the following mail thread:
http://www.mail-archive.com/l4-hackers@os.inf.tu-dresden.de/msg05162.html

Was 'foc_caps_equal.patch'
2013-07-16 12:23:13 +02:00
Sebastian Sumpf
0b7d91f663 ARM: Errata 743622
Restrict the appliance of ERRATA 743622 to CPU revisions: r2p0-r2p2.

Was 'foc_arm_errata.patch'
2013-07-16 12:23:13 +02:00
Sebastian Sumpf
4fe9467192 GDB monitor: Check for ARM breakpoint IP
Performed in 'slow_trapentry'. Was 'fix_exception_ip.patch'.
2013-07-16 12:23:13 +02:00
36 changed files with 559 additions and 35 deletions

349
COPYING-GPL-2 Normal file
View File

@@ -0,0 +1,349 @@
NOTE! This License shall not affect user programs that use the micro-kernel
API to invoke kernel-operations or services provided in other address
spaces - this is merely considered normal use of the kernel or
accompanying user-level services, and does not fall under the heading of
"derivative work".
-----------------------------------------------------------------------
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Public License instead of this License.

View File

@@ -730,6 +730,14 @@ config POWERSAVE_GETCHAR
prevent some P4 processors from being overheated. This option
requires a working timer IRQ to wakeup getchar periodically.
config USER_SINGLE_STEP
bool "Enable user level single stepping support"
depends on IA32
default n
help
This option enables single stepping of user level applications outside of
JDB.
choice
prompt "Warn levels"
default WARN_WARNING

View File

@@ -23,7 +23,7 @@ public:
static Cpu_phys_id cpu_id();
};
INTERFACE[arm && !arm_em_tz]:
INTERFACE[arm && !arm_em_tz && !arm_em_ns]:
EXTENSION class Proc
{
@@ -53,6 +53,21 @@ public:
};
};
INTERFACE[arm && arm_em_ns]:
EXTENSION class Proc
{
public:
enum : unsigned
{
Cli_mask = Status_IRQ_disabled,
Sti_mask = Status_IRQ_disabled,
Status_preempt_disabled = Status_IRQ_disabled,
Status_interrupts_mask = Status_IRQ_disabled,
Status_always_mask = Status_FIQ_disabled,
};
};
IMPLEMENTATION[arm]:
#include "types.h"
@@ -75,7 +90,8 @@ void Proc::stack_pointer(Mword sp)
IMPLEMENT static inline
Mword Proc::program_counter()
{
register Mword pc asm ("pc");
Mword pc;
asm ("mov %0, pc" : "=r" (pc));
return pc;
}

View File

@@ -43,7 +43,7 @@ IMPLEMENTATION:
enum
{
Name_buffer_size = 8192,
Name_buffer_size = 4*8192,
Name_entries = Name_buffer_size / sizeof(Jdb_kobject_name),
};

View File

@@ -43,6 +43,13 @@ config PF_IMX_6
help
Choose for i.MX6 platform.
config PF_IMX_53
bool "i.MX53"
depends on PF_IMX
select CAN_ARM_CPU_CORTEX_A8
help
Choose for i.MX53
endchoice
config PF_IMX_RAM_PHYS_BASE
@@ -50,4 +57,5 @@ config PF_IMX_RAM_PHYS_BASE
default 0xc0000000 if PF_IMX_21
default 0x80000000 if PF_IMX_35
default 0x90000000 if PF_IMX_51
default 0x10000000 if PF_IMX_6
default 0x70000000 if PF_IMX_53
default 0x10000000 if PF_IMX_6

View File

@@ -9,10 +9,12 @@ PREPROCESS_PARTS += $(if $(CONFIG_PF_IMX_51),imx51 imx_epit \
pic_gic pic_gic_mxc_tzic)
PREPROCESS_PARTS += $(if $(CONFIG_PF_IMX_53),imx53 imx_epit \
pic_gic pic_gic_mxc_tzic)
PREPROCESS_PARTS += $(if $(CONFIG_PF_IMX_6),imx6 pic_gic mptimer)
RAM_PHYS_BASE := $(CONFIG_PF_IMX_RAM_PHYS_BASE)
INTERFACES_KERNEL += $(if $(CONFIG_PF_IMX_51),gic)
INTERFACES_KERNEL += $(if $(CONFIG_PF_IMX_53),gic)
INTERFACES_KERNEL += $(if $(CONFIG_PF_IMX_6),gic)
INTERFACES_KERNEL-$(CONFIG_PF_IMX_35) += timer_imx_epit
INTERFACES_KERNEL-$(CONFIG_PF_IMX_51) += timer_imx_epit
@@ -28,6 +30,7 @@ pic_IMPL += $(if $(CONFIG_PF_IMX_35),pic-arm-imx)
pic_IMPL += $(if $(CONFIG_PF_IMX_51),pic-gic pic-arm-imx51)
pic_IMPL += $(if $(CONFIG_PF_IMX_53),pic-gic pic-arm-imx51)
pic_IMPL += $(if $(CONFIG_PF_IMX_6),pic-gic pic-arm-imx51)
bootstrap_IMPL += bootstrap-arm-imx
timer_IMPL += $(if $(CONFIG_PF_IMX_21),timer-arm-imx21)
timer_IMPL += $(if $(CONFIG_PF_IMX_35),timer-arm-imx_epit)

View File

@@ -83,3 +83,4 @@ public:
Uart_phys_base = Uart2_phys_base,
};
};

View File

@@ -4,5 +4,13 @@ INTERFACE [arm && mptimer && omap4_pandaboard]:
EXTENSION class Timer
{
private:
static Mword interval() { return 499999; }
static Mword interval()
{
/*
* This is only valid for Panda A6, as we run it at our offices. For A6
* U-Boot will clock the board at 800 MHz leading to a 400 MHz private timer
* tick.
*/
return 399999;
}
};

View File

@@ -40,6 +40,7 @@ public:
Copro_dbg_model_v6 = 2,
Copro_dbg_model_v6_1 = 3,
Copro_dbg_model_v7 = 4,
Copro_dbg_model_v7_1 = 5,
};
unsigned copro_dbg_model() const { return _cpu_id._dfr0 & 0xf; }
@@ -498,7 +499,7 @@ Cpu::id_init()
}
//---------------------------------------------------------------------------
IMPLEMENTATION [!arm_cpu_errata || !armv6plus]:
IMPLEMENTATION [!arm_cpu_errata || !armv6plus || omap4_pandaboard]:
PRIVATE static inline
void Cpu::init_errata_workarounds() {}
@@ -559,8 +560,8 @@ Cpu::init_errata_workarounds()
if (rev == 0x20 || rev == 0x21 || rev == 0x22)
set_c15_c0_1((1 << 12) | (1 << 22));
// errata: 743622
if ((rev & 0xf0) == 0x20)
// errata: 743622 (r2p0 - r2p2)
if ((rev & 0xf0) == 0x20 && (rev & 0xf) < 0x3)
set_c15_c0_1(1 << 6);
// errata: 751472

View File

@@ -113,7 +113,7 @@ Mem_op::arm_mem_cache_maint(int op, void const *start, void const *end)
case Op_cache_dma_coherent:
{
Mem_unit::flush_dcache(Virt_addr(Address(start)), Virt_addr(Address(end)));
Mem_unit::flush_dcache(start, end);
outer_cache_op(Op_cache_l2_flush, Address(start), Address(end));
}
break;

View File

@@ -261,6 +261,7 @@ Perf_cnt::init_cpu()
//set_event_type(0, EVENT_EXTMEM_TRANSFER_READ);
//set_event_type(1, EVENT_EXTMEM_TRANSFER_WRITE);
#if 0
set_event_type(3, EVENT_EXTMEM_TRANSFER_READ);
set_event_type(4, EVENT_LINE_MIGRATION);
@@ -296,7 +297,8 @@ int Perf_cnt::_nr_counters;
PRIVATE static
bool
Perf_cnt::is_avail()
{ return Cpu::boot_cpu()->copro_dbg_model() == Cpu::Copro_dbg_model_v7; }
{ return Cpu::boot_cpu()->copro_dbg_model() == Cpu::Copro_dbg_model_v7 ||
Cpu::boot_cpu()->copro_dbg_model() == Cpu::Copro_dbg_model_v7_1; }
PRIVATE static
void

View File

@@ -43,8 +43,8 @@ Sys_call_page::init()
Vmem_alloc::NO_ZERO_FILL, Vmem_alloc::User))
panic("FIASCO: can't allocate system-call page.\n");
for (unsigned i = 0; i < Config::PAGE_SIZE; i += sizeof(Mword))
*(sys_calls++) = 0xef000000; // svc
for (unsigned i = 0; i < Config::PAGE_SIZE / sizeof(Mword); i++)
sys_calls[i] = 0xef000000; // svc
set_utcb_get_code((Mword*)(Mem_layout::Syscalls + 0xf00));

View File

@@ -316,6 +316,10 @@ extern "C" {
if (handle_copro_fault[copro](opcode, ts))
return;
}
/* check for ARM default GDB breakpoint */
if (!(ts->psr & Proc::Status_thumb) && opcode == 0xe7ffdefe)
ts->pc -= 4;
}
undef_insn:
@@ -415,7 +419,7 @@ Thread::user_ip() const
IMPLEMENT inline
Mword
Thread::user_flags() const
{ return 0; }
{ return state() & Thread_ready; }
IMPLEMENT inline NEEDS[Thread::exception_triggered]
void
@@ -501,7 +505,17 @@ Thread::copy_utcb_to_ts(L4_msg_tag const &tag, Thread *snd, Thread *rcv,
}
else
{
Mem::memcpy_mwords (ts, snd_utcb->values, s > 19 ? 19 : s);
/*
* copy R0..R12,SP,LR,PC,PSR (UTCB Mwords 3..15,16,17,19,20)
* don't allow to overwrite pf_address, error_code, tpidruro, km_lr
* (these might have changed in the kernel without the Genode exception
* handler knowing about it, so it could try to restore outdated values)
*/
Mem::memcpy_mwords (&ts->r[0], &snd_utcb->values[3], s > 15 ? 13 : s);
if (EXPECT_TRUE(s > 16))
ts->usp = snd_utcb->values[16];
if (EXPECT_TRUE(s > 17))
ts->ulr = snd_utcb->values[17];
if (EXPECT_TRUE(s > 19))
ts->pc = snd_utcb->values[19];
if (EXPECT_TRUE(s > 20))
@@ -614,6 +628,10 @@ Thread::condition_valid(Unsigned32 insn, Unsigned32 psr)
return (v[insn >> 28] >> (psr >> 28)) & 1;
}
IMPLEMENT inline
void Thread::user_single_step(bool)
{}
// ------------------------------------------------------------------------
IMPLEMENTATION [arm && armv6plus]:

View File

@@ -59,7 +59,7 @@ _tramp_mp_entry:
msr cpsr_c, r0
// enable SMP
#ifndef CONFIG_ARM_EM_NS
#if !defined(CONFIG_ARM_EM_NS) && !defined(CONFIG_ARM_CORTEX_A15)
adr r0, .Lmpcore_phys_base
ldr r0, [r0]
ldr r1, [r0]

View File

@@ -246,8 +246,8 @@ void Config::init()
esc_hack = true;
#ifdef CONFIG_SERIAL
if ( Koptions::o()->opt(Koptions::F_serial_esc)
&& !Koptions::o()->opt(Koptions::F_noserial)
if ( /*Koptions::o()->opt(Koptions::F_serial_esc)
&&*/ !Koptions::o()->opt(Koptions::F_noserial)
# ifdef CONFIG_KDB
&& Koptions::o()->opt(Koptions::F_nokdb)
# endif

View File

@@ -46,6 +46,30 @@
jmp slowtraps
.endm
#ifdef CONFIG_USER_SINGLE_STEP
.macro HANDLE_USER_TRAP1
/* Save EFLAGS, this may trap if user task had single stepping activated
* test for single stepping
*/
pushf
addl $4, %esp
testl $EFLAGS_TF, -4(%esp)
.endm
.macro RESTORE_USER_TRAP1
/* Restore single stepping if it has been set */
je 1f
orl $EFLAGS_TF, (%esp)
1:
.endm
#else
.macro HANDLE_USER_TRAP1
.endm
.macro RESTORE_USER_TRAP1
.endm
#endif
.p2align 4
.globl entry_vec01_debug
entry_vec01_debug:
@@ -59,6 +83,15 @@ entry_vec01_debug:
cmpl $entry_sys_fast_ipc_log, (%esp)
je 2f
#endif
/* test if trap was raised within kernel */
testl $3, 4(%esp)
jne 1f
/* turn of EFLAGS.TF */
btrl $7, 8(%esp)
iret
1: pushl $0
pushl $1
pusha
@@ -226,10 +259,16 @@ alien_sys_fast_ipc_log:
.p2align(4)
.global entry_sys_fast_ipc_c
entry_sys_fast_ipc_c:
HANDLE_USER_TRAP1
pop %esp
pushl $(GDT_DATA_USER|SEL_PL_U) /* user ss */
pushl %ebp // push user SP (get in ebp)
pushf // fake user eflags
RESTORE_USER_TRAP1
cld
// Fake user cs. This cs value is never used with exception
// that the thread is ex_regs'd before we leave with sysexit.

View File

@@ -79,6 +79,7 @@ Thread::copy_utcb_to_ts(L4_msg_tag const &tag, Thread *snd, Thread *rcv,
Trap_state *ts = (Trap_state*)rcv->_utcb_handler;
Mword s = tag.words();
Unsigned32 cs = ts->cs();
Unsigned32 eflags_tf = ts->flags() & EFLAGS_TF;
Utcb *snd_utcb = snd->utcb().access();
// XXX: check that gs and fs point to valid user_entry only, for gdt and
@@ -110,6 +111,13 @@ Thread::copy_utcb_to_ts(L4_msg_tag const &tag, Thread *snd, Thread *rcv,
// don't allow to overwrite the code selector!
ts->cs(cs);
/*
* don't allow to overwrite the single-step flag
* (it might have changed in the kernel without the Genode exception handler
* knowing about it, so it could try to restore an outdated value)
*/
ts->flags((ts->flags() & ~EFLAGS_TF) | eflags_tf);
bool ret = transfer_msg_items(tag, snd, snd_utcb,
rcv, rcv->utcb().access(), rights);

View File

@@ -414,6 +414,7 @@ GATE_INITTAB_END
.p2align
.globl leave_by_trigger_exception
leave_by_trigger_exception:
cli
sub $40, %rsp
pushq $0x00
pushq $0xff

View File

@@ -86,6 +86,12 @@ public:
// static const bool hlt_works_ok = false;
static bool hlt_works_ok;
#ifdef CONFIG_USER_SINGLE_STEP
static const bool user_single_step = true;
#else
static const bool user_single_step = false;
#endif
// the default uart to use for serial console
static const unsigned default_console_uart = 1;
static const unsigned default_console_uart_baudrate = 115200;

View File

@@ -92,7 +92,10 @@ Thread::user_ip() const
IMPLEMENT inline
Mword
Thread::user_flags() const
{ return regs()->flags(); }
{
// pass thread-ready state in carry flag (Thread_ready is bit 0)
return (regs()->flags() & ~Thread_ready) | (state() & Thread_ready);
}
/** Check if the pagefault occured at a special place: At some places in the
kernel we want to ensure that a specific address is mapped. The regular
@@ -188,6 +191,10 @@ Thread::handle_slow_trap(Trap_state *ts)
goto generic_debug;
}
if (Config::user_single_step && ts->_trapno == 1 && from_user)
if (send_exception(ts))
goto success;
if (from_user && _space.user_mode())
{
if (ts->_trapno == 14 && Kmem::is_io_bitmap_page_fault(ts->_cr2))
@@ -428,7 +435,8 @@ Thread::send_exception_arch(Trap_state *ts)
// thread (not alien) and it's a debug trap,
// debug traps for aliens are always reflected as exception IPCs
if (!(state() & Thread_alien)
&& (ts->_trapno == 1 || ts->_trapno == 3))
&& ((ts->_trapno == 1 && !Config::user_single_step)
|| ts->_trapno == 3))
return 0; // we do not handle this
if (ts->_trapno == 3)
@@ -500,6 +508,11 @@ Thread::user_ip(Mword ip)
}
}
IMPLEMENT inline
void
Thread::user_single_step(bool)
{}
//----------------------------------------------------------------------------
IMPLEMENTATION [(ia32,amd64,ux) && !io]:
@@ -852,3 +865,16 @@ PRIVATE static inline
int
Thread::call_nested_trap_handler(Trap_state *)
{ return -1; }
//---------------------------------------------------------------------------
IMPLEMENTATION [ia32]:
IMPLEMENT inline
void
Thread::user_single_step(bool enable)
{
if (!Config::user_single_step)
return;
regs()->flags(enable ? user_flags() | EFLAGS_TF : user_flags() & ~EFLAGS_TF);
}

View File

@@ -181,6 +181,7 @@ Kernel_thread::idle_op()
arch_tickless_idle(cpu);
enable_tlb(cpu);
Mem_unit::tlb_flush();
Rcu::leave_idle(cpu);
Timer_tick::enable(cpu);
}

View File

@@ -306,6 +306,10 @@ Thread::user_ip(Mword ip)
}
}
IMPLEMENT inline
void Thread::user_single_step(bool)
{}
PUBLIC inline NEEDS ["trap_state.h"]
int
Thread::send_exception_arch(Trap_state * /*ts*/)

View File

@@ -494,10 +494,12 @@ Task::sys_caps_equal(Syscall_frame *, Utcb *utcb)
if (obj_a.special() || obj_b.special())
return commit_result(obj_a.special_cap() == obj_b.special_cap());
Obj_space::Capability c_a = lookup(obj_a.cap());
Obj_space::Capability c_b = lookup(obj_b.cap());
Kobject_iface* ki_a = lookup(obj_a.cap()).obj();
Kobject_iface* ki_b = lookup(obj_b.cap()).obj();
Address a_a = ki_a ? ki_a->kobject_start_addr() : 0;
Address a_b = ki_b ? ki_b->kobject_start_addr() : 0;
return commit_result(c_a == c_b);
return commit_result(a_a == a_b);
}
PRIVATE inline NOEXPORT

View File

@@ -73,6 +73,7 @@ public:
{
Exr_cancel = 0x10000,
Exr_trigger_exception = 0x20000,
Exr_single_step = 0x40000,
};
enum Vcpu_ctl_flags
@@ -140,6 +141,8 @@ public:
inline Mword user_flags() const;
inline void user_single_step(bool);
/** nesting level in debugger (always critical) if >1 */
static Per_cpu<unsigned long> nested_trap_recover;
static void handle_remote_requests_irq() asm ("handle_remote_cpu_requests");

View File

@@ -529,6 +529,8 @@ Thread_object::ex_regs(Address ip, Address sp,
if (o_ip) *o_ip = user_ip();
if (o_flags) *o_flags = user_flags();
(ops & Exr_single_step) ? user_single_step(true) : user_single_step(false);
// Changing the run state is only possible when the thread is not in
// an exception.
if (!(ops & Exr_cancel) && (state() & Thread_in_exception))

View File

@@ -31,6 +31,7 @@ IMPLEMENTATION [debug && serial && !ux]:
#include "globals.h"
#include "kernel_console.h"
#include "keycodes.h"
#include "koptions.h"
#include "uart.h"
static Vkey::Echo_type vkey_echo;
@@ -116,7 +117,7 @@ Vkey::check_()
if (c == -1)
break;
if (c == KEY_ESC)
if ((c == KEY_ESC) && (Koptions::o()->opt(Koptions::F_serial_esc)))
{
ret = 0; // break into kernel debugger
break;

View File

@@ -51,9 +51,8 @@ FIASCO_DEFINE_KOBJ(Vlog);
PUBLIC
Vlog::Vlog()
: _irq(0),
_i_flags(F_ICRNL), _o_flags(F_ONLCR), _l_flags(F_ECHO)
_i_flags(F_ICRNL), _o_flags(F_ONLCR), _l_flags(0)
{
Vkey::set_echo(Vkey::Echo_crnl);
// CAP idx 5 is the initial kernel stream
initial_kobjects.register_obj(this, 5);
}

View File

@@ -290,13 +290,13 @@ Makeconf.bid.local-helper:
Makeconf.bid.local-internal-names:
ifneq ($(CONFIG_INT_CPP_NAME_SWITCH),)
$(VERBOSE) set -e; X="tmp.$$$$$$RANDOM.c" ; echo 'int main(void){}'>$$X ; \
$(VERBOSE) set -e; X="$(OBJ_DIR)/tmp.$$$$$$RANDOM.c" ; echo 'int main(void){}'>$$X ; \
rm -f $$X.out ; $(LD_GENDEP_PREFIX) GENDEP_SOURCE=$$X \
GENDEP_OUTPUT=$$X.out $(CC) $(CCXX_FLAGS) -c $$X -o $$X.o; \
test -e $$X.out; echo INT_CPP_NAME=`cat $$X.out` \
>>$(DROPSCONF_CONFIG_MK); \
rm -f $$X $$X.{o,out};
$(VERBOSE)set -e; X="tmp.$$$$$$RANDOM.cc" ; echo 'int main(void){}'>$$X; \
$(VERBOSE)set -e; X="$(OBJ_DIR)/tmp.$$$$$$RANDOM.cc" ; echo 'int main(void){}'>$$X; \
rm -f $$X.out; $(LD_GENDEP_PREFIX) GENDEP_SOURCE=$$X \
GENDEP_OUTPUT=$$X.out $(CXX) -c $$X -o $$X.o; \
test -e $$X.out; echo INT_CXX_NAME=`cat $$X.out` \
@@ -393,7 +393,6 @@ define switch_ram_base_func
echo "# File semi-automatically generated by 'make switch_ram_base'" > $(OBJ_BASE)/Makeconf.ram_base; \
echo "RAM_BASE := $(1)" >> $(OBJ_BASE)/Makeconf.ram_base; \
PWD=$(PWD)/pkg/sigma0/server/src $(MAKE) RAM_BASE=$(1) -C pkg/sigma0/server/src; \
PWD=$(PWD)/pkg/moe/server/src $(MAKE) RAM_BASE=$(1) -C pkg/moe/server/src; \
echo "RAM_BASE_SWITCH_OK := yes" >> $(OBJ_BASE)/Makeconf.ram_base
endef

View File

@@ -0,0 +1,4 @@
PLATFORM_NAME = "Freescale i.MX53"
PLATFORM_ARCH = arm
PLATFORM_RAM_BASE = 0x70000000
PLATFORM_RAM_SIZE_MB = 1024

View File

@@ -17,6 +17,7 @@ SUPPORT_CC_arm-imx21 := platform/imx.cc
DEFAULT_RELOC_arm-imx21 := 0x00200000 # because of blob
SUPPORT_CC_arm-imx35 := platform/imx.cc
SUPPORT_CC_arm-imx51 := platform/imx.cc
SUPPORT_CC_arm-imx53 := platform/imx.cc
SUPPORT_CC_arm-imx6 := platform/imx.cc
SUPPORT_CC_arm-om := platform/om.cc
SUPPORT_CC_arm-kirkwood := platform/kirkwood.cc

View File

@@ -17,8 +17,6 @@
#include "support.h"
#include <l4/drivers/uart_s3c2410.h>
#include <cstdio>
namespace {
class Platform_arm_exynos : public Platform_single_region_ram
{

View File

@@ -36,6 +36,9 @@ class Platform_arm_imx : public Platform_single_region_ram
#elif defined(PLATFORM_TYPE_imx51)
static L4::Io_register_block_mmio r(0x73fbc000);
static L4::Uart_imx51 _uart;
#elif defined(PLATFORM_TYPE_imx53)
static L4::Io_register_block_mmio r(0x53fbc000);
static L4::Uart_imx51 _uart;
#elif defined(PLATFORM_TYPE_imx6)
//static L4::Io_register_block_mmio r(0x02020000); // UART1
static L4::Io_register_block_mmio r(0x021e8000); // UART2

View File

@@ -612,8 +612,15 @@ public:
printf("PCI IO port = %x\n", comport);
}
if (comport == -1)
comport = 1;
if (comport == -1) {
/* try to read Bios Data Area (BDA) to get comport information */
unsigned short comport_count = (*((unsigned short *)0x410) >> 9) & 0x7;
if (comport_count)
comport = *((unsigned short *)0x400);
else
/* give up and try default values */
comport = 1;
}
if (init_uart(comport, comirq, &du))
printf("UART init failed\n");

View File

@@ -9,7 +9,7 @@ REQUIRES_LIBS = libc_minimal cxx_util cxx_io cxx_base \
DEFINES += -DL4_MINIMAL_LIBC
DEFAULT_RELOC_x86 := 0x00100000
DEFAULT_RELOC_amd64 := 0x00100000
DEFAULT_RELOC_arm := 0x00090000
DEFAULT_RELOC_arm := 0x000a0000
DEFAULT_RELOC_sparc := 0x01200000
DEFAULT_RELOC_ppc32 := 0x00100000
RELOC_PHYS := y

View File

@@ -27,6 +27,7 @@
#include "ioports.h"
#include "mem_man_test.h"
#include <l4/sys/debugger.h>
#include <l4/sys/scheduler.h>
/* started as the L4 sigma0 task from crt0.S */
@@ -61,6 +62,10 @@ init(l4_kernel_info_t *info)
l4_debugger_set_object_name(L4_BASE_FACTORY_CAP, "root factory");
l4_debugger_set_object_name(L4_BASE_THREAD_CAP, "sigma0");
l4_sched_param_t params = l4_sched_param(255);
l4_scheduler_run_thread(L4_BASE_SCHEDULER_CAP, L4_BASE_THREAD_CAP, &params);
Page_alloc_base::init();
init_memory(info);

View File

@@ -39,8 +39,9 @@ void handle_io_page_fault(l4_umword_t t, l4_utcb_t *utcb, Answer *a)
size = l4_fpage_size(fp) + PORT_SHIFT;
unsigned long i = io_ports.alloc(Region::bs(port, 1UL << size, t));
if (i == port)
if (i == port) {
a->snd_fpage(l4_iofpage(port >> PORT_SHIFT, size - PORT_SHIFT));
else
a->tag = l4_msgtag(0, 0, 1, 0);
} else
a->error(L4_ENOMEM);
}