Stefan Kalkowski
committed by
Norman Feske
Norman Feske
parent
dd15d65800
commit
9c7df24e20
104
include/regulator/component.h
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104
include/regulator/component.h
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@@ -0,0 +1,104 @@
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/*
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* \brief Regulator-session component
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* \author Stefan Kalkowski
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* \date 2013-06-13
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__REGULATOR__COMPONENT_H_
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#define _INCLUDE__REGULATOR__COMPONENT_H_
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#include <root/component.h>
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#include <regulator_session/rpc_object.h>
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#include <regulator/driver.h>
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namespace Regulator {
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class Session_component;
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class Root;
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}
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class Regulator::Session_component : public Regulator::Session_rpc_object
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{
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private:
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Driver_factory & _driver_factory;
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Driver & _driver;
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public:
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Session_component(Regulator_id regulator_id,
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Driver_factory & driver_factory)
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: Session_rpc_object(regulator_id),
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_driver_factory(driver_factory),
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_driver(_driver_factory.create(regulator_id)) { }
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~Session_component()
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{
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_driver.state(_id, false);
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_driver_factory.destroy(_driver);
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}
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/***********************************
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** Regulator session interface **
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***********************************/
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void level(unsigned long level) override { _driver.level(_id, level); }
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unsigned long level() override { return _driver.level(_id); }
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void state(bool enable) override { _driver.state(_id, enable); }
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bool state() override { return _driver.state(_id); }
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};
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class Regulator::Root :
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public Genode::Root_component<Regulator::Session_component>
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{
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private:
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Regulator::Driver_factory & _driver_factory;
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protected:
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Session_component *_create_session(const char *args) override
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{
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using namespace Genode;
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char reg_name[64];
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Arg_string::find_arg(args, "regulator").string(reg_name,
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sizeof(reg_name), 0);
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size_t ram_quota =
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Arg_string::find_arg(args, "ram_quota").ulong_value(0);
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/* delete ram quota by the memory needed for the session */
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size_t session_size = max((size_t)4096,
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sizeof(Session_component));
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if (ram_quota < session_size)
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throw Insufficient_ram_quota();
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if (!strlen(reg_name))
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throw Service_denied();
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return new (md_alloc())
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Session_component(regulator_id_by_name(reg_name),
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_driver_factory);
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}
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public:
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Root(Genode::Env & env,
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Genode::Allocator & md_alloc,
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Regulator::Driver_factory & driver_factory)
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: Genode::Root_component<Regulator::Session_component>(env.ep(),
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md_alloc),
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_driver_factory(driver_factory) { }
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};
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#endif /* _INCLUDE__REGULATOR__COMPONENT_H_ */
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54
include/regulator/driver.h
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54
include/regulator/driver.h
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@@ -0,0 +1,54 @@
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/*
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* \brief Regulator-driver interface
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* \author Stefan Kalkowski
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* \date 2013-06-13
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__REGULATOR__DRIVER_H_
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#define _INCLUDE__REGULATOR__DRIVER_H_
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#include <regulator/consts.h>
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namespace Regulator {
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struct Driver;
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struct Driver_factory;
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}
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/**
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* Interface to be implemented by the device-specific driver code
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*/
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struct Regulator::Driver : Genode::Interface
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{
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virtual void level(Regulator_id id, unsigned long level) = 0;
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virtual unsigned long level(Regulator_id id) = 0;
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virtual void state(Regulator_id id, bool enable) = 0;
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virtual bool state(Regulator_id id) = 0;
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};
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/**
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* Interface for constructing the driver object
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*/
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struct Regulator::Driver_factory : Genode::Interface
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{
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/**
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* Construct new driver
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*/
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virtual Driver &create(Regulator_id regulator) = 0;
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/**
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* Destroy driver
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*/
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virtual void destroy(Driver &driver) = 0;
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};
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#endif /* _REGULATOR__DRIVER_H_ */
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22
include/regulator_session/capability.h
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22
include/regulator_session/capability.h
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@@ -0,0 +1,22 @@
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/*
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* \brief Regulator session capability type
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* \author Stefan Kalkowski
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* \date 2013-06-13
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__REGULATOR_SESSION__CAPABILITY_H_
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#define _INCLUDE__REGULATOR_SESSION__CAPABILITY_H_
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#include <base/capability.h>
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#include <regulator_session/regulator_session.h>
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namespace Regulator { typedef Genode::Capability<Session> Session_capability; }
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#endif /* _INCLUDE__REGULATOR_SESSION__CAPABILITY_H_ */
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44
include/regulator_session/client.h
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44
include/regulator_session/client.h
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@@ -0,0 +1,44 @@
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/*
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* \brief Client-side regulator session interface
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* \author Stefan Kalkowski
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* \date 2013-06-13
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__REGULATOR_SESSION__CLIENT_H_
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#define _INCLUDE__REGULATOR_SESSION__CLIENT_H_
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#include <base/rpc_client.h>
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#include <regulator_session/capability.h>
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namespace Regulator { struct Session_client; }
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struct Regulator::Session_client : public Genode::Rpc_client<Session>
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{
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/**
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* Constructor
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*
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* \param session session capability
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*/
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Session_client(Session_capability session)
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: Genode::Rpc_client<Session>(session) { }
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/*********************************
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** Regulator session interface **
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*********************************/
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void level(unsigned long level) override { call<Rpc_set_level>(level); }
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unsigned long level() override { return call<Rpc_level>(); }
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void state(bool enable) override { call<Rpc_set_state>(enable); }
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bool state() override { return call<Rpc_state>(); }
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};
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#endif /* _INCLUDE__REGULATOR_SESSION__CLIENT_H_ */
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42
include/regulator_session/connection.h
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42
include/regulator_session/connection.h
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@@ -0,0 +1,42 @@
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/*
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* \brief Connection to regulator service
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* \author Stefan Kalkowski
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* \date 2013-06-13
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__REGULATOR_SESSION__CONNECTION_H_
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#define _INCLUDE__REGULATOR_SESSION__CONNECTION_H_
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#include <regulator_session/client.h>
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#include <regulator/consts.h>
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#include <base/connection.h>
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namespace Regulator { struct Connection; }
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struct Regulator::Connection : Genode::Connection<Session>, Session_client
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{
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/**
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* Constructor
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*
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* \param regulator identifier for the specific regulator
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* \param label string identifier of the client
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*/
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Connection(Genode::Env &env, Regulator_id regulator, const char * label = "")
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:
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Genode::Connection<Session>(env,
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session(env.parent(),
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"ram_quota=8K, cap_quota=%ld, regulator=\"%s\", label=\"%s\"",
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CAP_QUOTA, regulator_name_by_id(regulator), label)),
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Session_client(cap())
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{ }
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};
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#endif /* _INCLUDE__REGULATOR_SESSION__CONNECTION_H_ */
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65
include/regulator_session/regulator_session.h
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65
include/regulator_session/regulator_session.h
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@@ -0,0 +1,65 @@
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/*
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* \brief Abstract regulator session interface.
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* \author Stefan Kalkowski
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* \date 2013-06-13
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__REGULATOR_SESSION__REGULATOR_SESSION_H_
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#define _INCLUDE__REGULATOR_SESSION__REGULATOR_SESSION_H_
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#include <session/session.h>
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namespace Regulator { struct Session; }
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struct Regulator::Session : public Genode::Session
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{
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/**
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* \noapi
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*/
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static const char *service_name() { return "Regulator"; }
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enum { CAP_QUOTA = 2 };
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virtual ~Session() { }
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/**
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* Set regulator specific level
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*/
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virtual void level(unsigned long level) = 0;
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/**
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* Returns current regulator level
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*/
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virtual unsigned long level() = 0;
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/**
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* Enable/disable regulator
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*/
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virtual void state(bool enable) = 0;
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/**
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* Returns whether regulator is enabled or not
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*/
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virtual bool state() = 0;
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/*******************
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** RPC interface **
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*******************/
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GENODE_RPC(Rpc_set_level, void, level, unsigned long);
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GENODE_RPC(Rpc_level, unsigned long, level);
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GENODE_RPC(Rpc_set_state, void, state, bool);
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GENODE_RPC(Rpc_state, bool, state);
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GENODE_RPC_INTERFACE(Rpc_set_level, Rpc_level, Rpc_set_state, Rpc_state);
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};
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#endif /* _INCLUDE__REGULATOR_SESSION__REGULATOR_SESSION_H_ */
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40
include/regulator_session/rpc_object.h
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40
include/regulator_session/rpc_object.h
Normal file
@@ -0,0 +1,40 @@
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/*
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* \brief Server-side block regulator interface
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* \author Stefan Kalkowski
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* \date 2013-06-13
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__REGULATOR_SESSION__SERVER_H_
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#define _INCLUDE__REGULATOR_SESSION__SERVER_H_
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#include <base/rpc_server.h>
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#include <regulator/consts.h>
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#include <regulator_session/regulator_session.h>
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namespace Regulator { class Session_rpc_object; }
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class Regulator::Session_rpc_object : public Genode::Rpc_object<Session, Session_rpc_object>
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{
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protected:
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Regulator_id _id; /* regulator identifier */
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public:
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/**
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* Constructor
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*
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* \param id identifies the specific regulator
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*/
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Session_rpc_object(Regulator_id id) : _id(id) { }
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};
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#endif /* _INCLUDE__REGULATOR_SESSION__SERVER_H_ */
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86
include/spec/exynos5/regulator/consts.h
Normal file
86
include/spec/exynos5/regulator/consts.h
Normal file
@@ -0,0 +1,86 @@
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/*
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* \brief Regulator definitions for Exynos5
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
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* \date 2013-06-13
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__SPEC__EXYNOS5__REGULATOR__CONSTS_H_
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#define _INCLUDE__SPEC__EXYNOS5__REGULATOR__CONSTS_H_
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#include <util/string.h>
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namespace Regulator {
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enum Regulator_id {
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CLK_CPU,
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CLK_SATA,
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CLK_USB30,
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CLK_USB20,
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CLK_MMC0,
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CLK_HDMI,
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PWR_SATA,
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PWR_USB30,
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PWR_USB20,
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PWR_HDMI,
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MAX,
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INVALID
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};
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struct Regulator_name {
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Regulator_id id;
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const char * name;
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};
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static constexpr Regulator_name names[] = {
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{ CLK_CPU, "clock-cpu" },
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{ CLK_SATA, "clock-sata" },
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{ CLK_USB30, "clock-usb3.0" },
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{ CLK_USB20, "clock-usb2.0" },
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{ CLK_MMC0, "clock-mmc0" },
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{ CLK_HDMI, "clock-hdmi" },
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{ PWR_SATA, "power-sata" },
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{ PWR_USB30, "power-usb3.0" },
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{ PWR_USB20, "power-usb2.0" },
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{ PWR_HDMI, "power-hdmi"},
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};
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inline Regulator_id regulator_id_by_name(const char * name)
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{
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for (unsigned i = 0; i < sizeof(names)/sizeof(names[0]); i++)
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if (Genode::strcmp(names[i].name, name) == 0)
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return names[i].id;
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return INVALID;
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}
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inline const char * regulator_name_by_id(Regulator_id id) {
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return (id < sizeof(names)/sizeof(names[0])) ? names[id].name : 0; }
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||||
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||||
/***************************************
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||||
** Device specific level definitions **
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||||
***************************************/
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enum Cpu_clock_freq {
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CPU_FREQ_200 = 200000000,
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CPU_FREQ_400 = 400000000,
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CPU_FREQ_600 = 600000000,
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CPU_FREQ_800 = 800000000,
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||||
CPU_FREQ_1000 = 1000000000,
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CPU_FREQ_1200 = 1200000000,
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CPU_FREQ_1400 = 1400000000,
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CPU_FREQ_1600 = 1600000000,
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CPU_FREQ_1700 = 1700000000,
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||||
/* warning: 1700 not recommended by the reference manual
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||||
we just insert this for performance measurement against
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Linux, which uses this overclocking */
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||||
};
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||||
}
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||||
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||||
#endif /* _INCLUDE__SPEC__EXYNOS5__REGULATOR__CONSTS_H_ */
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21
lib/mk/spec/arm_v7/bootstrap-hw-arndale.mk
Normal file
21
lib/mk/spec/arm_v7/bootstrap-hw-arndale.mk
Normal file
@@ -0,0 +1,21 @@
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INC_DIR += $(REP_DIR)/src/bootstrap/spec/arndale
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INC_DIR += $(REP_DIR)/src/include
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SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
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SRC_CC += bootstrap/spec/arm/gicv2.cc
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SRC_CC += bootstrap/spec/arndale/platform.cc
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SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
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SRC_CC += hw/spec/32bit/memory_map.cc
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SRC_S += bootstrap/spec/arm/crt0.s
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||||
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||||
NR_OF_CPUS = 2
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||||
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||||
#
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||||
# we need more specific compiler hints for some 'special' assembly code
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||||
# override -march=armv7-a because it conflicts with -mcpu=cortex-a15
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||||
#
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||||
CC_MARCH = -mcpu=cortex-a15 -mfpu=vfpv3 -mfloat-abi=softfp
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||||
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||||
include $(call select_from_repositories,lib/mk/bootstrap-hw.inc)
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||||
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||||
vpath bootstrap/spec/arndale/platform.cc $(REP_DIR)/src
|
||||
10
lib/mk/spec/arm_v7/bootstrap-hw-odroid_xu.mk
Normal file
10
lib/mk/spec/arm_v7/bootstrap-hw-odroid_xu.mk
Normal file
@@ -0,0 +1,10 @@
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||||
INC_DIR += $(REP_DIR)/src/bootstrap/spec/odroid_xu
|
||||
|
||||
SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
|
||||
SRC_CC += bootstrap/spec/arm/gicv2.cc
|
||||
SRC_CC += bootstrap/spec/odroid_xu/platform.cc
|
||||
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
|
||||
SRC_CC += hw/spec/32bit/memory_map.cc
|
||||
SRC_S += bootstrap/spec/arm/crt0.s
|
||||
|
||||
include $(call select_from_repositories,lib/mk/bootstrap-hw.inc)
|
||||
34
lib/mk/spec/arm_v7/core-hw-arndale.mk
Normal file
34
lib/mk/spec/arm_v7/core-hw-arndale.mk
Normal file
@@ -0,0 +1,34 @@
|
||||
#
|
||||
# \brief Build config for Genodes core process
|
||||
# \author Stefan Kalkowski
|
||||
# \date 2015-02-09
|
||||
#
|
||||
|
||||
# add include paths
|
||||
INC_DIR += $(REP_DIR)/src/core/spec/arndale
|
||||
INC_DIR += $(REP_DIR)/src/core/spec/arm/virtualization
|
||||
INC_DIR += $(REP_DIR)/src/include
|
||||
|
||||
# add C++ sources
|
||||
SRC_CC += kernel/vm_thread_on.cc
|
||||
SRC_CC += spec/arm/gicv2.cc
|
||||
SRC_CC += spec/arm/virtualization/gicv2.cc
|
||||
SRC_CC += spec/arm_v7/virtualization/kernel/vm.cc
|
||||
SRC_CC += spec/arm/virtualization/platform_services.cc
|
||||
SRC_CC += spec/arm/virtualization/vm_session_component.cc
|
||||
SRC_CC += vm_session_common.cc
|
||||
SRC_CC += vm_session_component.cc
|
||||
|
||||
# add assembly sources
|
||||
SRC_S += spec/arm_v7/virtualization/exception_vector.s
|
||||
|
||||
NR_OF_CPUS = 2
|
||||
|
||||
#
|
||||
# we need more specific compiler hints for some 'special' assembly code
|
||||
# override -march=armv7-a because it conflicts with -mcpu=cortex-a15
|
||||
#
|
||||
CC_MARCH = -mcpu=cortex-a15 -mfpu=vfpv3 -mfloat-abi=softfp
|
||||
|
||||
# include less specific configuration
|
||||
include $(REP_DIR)/lib/mk/spec/arm_v7/core-hw-exynos5.inc
|
||||
20
lib/mk/spec/arm_v7/core-hw-exynos5.inc
Normal file
20
lib/mk/spec/arm_v7/core-hw-exynos5.inc
Normal file
@@ -0,0 +1,20 @@
|
||||
#
|
||||
# \brief Build config for Genodes core process
|
||||
# \author Martin Stein
|
||||
# \date 2011-12-16
|
||||
#
|
||||
|
||||
TMP := $(call select_from_repositories,lib/mk/core-hw.inc)
|
||||
BASE_HW_DIR := $(TMP:%lib/mk/core-hw.inc=%)
|
||||
|
||||
# add include paths
|
||||
INC_DIR += $(REP_DIR)/src/core
|
||||
INC_DIR += $(BASE_HW_DIR)/src/core/spec/exynos5
|
||||
|
||||
# add C++ sources
|
||||
SRC_CC += spec/arm/exynos_mct.cc
|
||||
|
||||
# include less specific configuration
|
||||
include $(BASE_HW_DIR)/lib/mk/spec/cortex_a15/core-hw.inc
|
||||
|
||||
vpath spec/arm/exynos_mct.cc ${REP_DIR}/src/core
|
||||
17
lib/mk/spec/arm_v7/core-hw-odroid_xu.mk
Normal file
17
lib/mk/spec/arm_v7/core-hw-odroid_xu.mk
Normal file
@@ -0,0 +1,17 @@
|
||||
#
|
||||
# \brief Build config for Genodes core process
|
||||
# \author Stefan Kalkowski
|
||||
# \date 2015-02-09
|
||||
#
|
||||
|
||||
# add include paths
|
||||
INC_DIR += $(REP_DIR)/src/core/spec/odroid_xu
|
||||
INC_DIR += $(REP_DIR)/src/include
|
||||
|
||||
# add C++ sources
|
||||
SRC_CC += spec/arm/gicv2.cc
|
||||
SRC_CC += kernel/vm_thread_off.cc
|
||||
SRC_CC += platform_services.cc
|
||||
|
||||
# include less specific configuration
|
||||
include $(REP_DIR)/lib/mk/spec/arm_v7/core-hw-exynos5.inc
|
||||
3
mk/spec/arndale.mk
Normal file
3
mk/spec/arndale.mk
Normal file
@@ -0,0 +1,3 @@
|
||||
SPECS += arm_v7a framebuffer usb
|
||||
|
||||
include $(call select_from_repositories,mk/spec/arm_v7a.mk)
|
||||
5
mk/spec/exynos5.mk
Normal file
5
mk/spec/exynos5.mk
Normal file
@@ -0,0 +1,5 @@
|
||||
SPECS += arm_v7a framebuffer usb
|
||||
|
||||
REP_INC_DIR += include/spec/exynos5
|
||||
|
||||
include $(BASE_DIR)/mk/spec/arm_v7a.mk
|
||||
4
mk/spec/odroid_xu.mk
Normal file
4
mk/spec/odroid_xu.mk
Normal file
@@ -0,0 +1,4 @@
|
||||
SPECS += arm_v7a
|
||||
|
||||
include $(call select_from_repositories,mk/spec/arm_v7a.mk)
|
||||
|
||||
9
recipes/src/base-hw-arndale/content.mk
Normal file
9
recipes/src/base-hw-arndale/content.mk
Normal file
@@ -0,0 +1,9 @@
|
||||
ARCH := arm_v7
|
||||
BOARD := arndale
|
||||
|
||||
content: lib/mk/spec/arm_v7/core-hw-exynos5.inc
|
||||
|
||||
lib/mk/spec/arm_v7/core-hw-exynos5.inc: lib/mk
|
||||
cp -r $(REP_DIR)/$@ $@
|
||||
|
||||
include $(REP_DIR)/recipes/src/base-hw_content.inc
|
||||
1
recipes/src/base-hw-arndale/hash
Normal file
1
recipes/src/base-hw-arndale/hash
Normal file
@@ -0,0 +1 @@
|
||||
2020-04-08 2390004bdcae04c78423af03c463c3a5a9d5fc4f
|
||||
2
recipes/src/base-hw-arndale/used_apis
Normal file
2
recipes/src/base-hw-arndale/used_apis
Normal file
@@ -0,0 +1,2 @@
|
||||
base-hw
|
||||
base
|
||||
9
recipes/src/base-hw-odroid_xu/content.mk
Normal file
9
recipes/src/base-hw-odroid_xu/content.mk
Normal file
@@ -0,0 +1,9 @@
|
||||
ARCH := arm_v7
|
||||
BOARD := odroid_xu
|
||||
|
||||
content: lib/mk/spec/arm_v7/core-hw-exynos5.inc
|
||||
|
||||
lib/mk/spec/arm_v7/core-hw-exynos5.inc: lib/mk
|
||||
cp -r $(REP_DIR)/$@ $@
|
||||
|
||||
include $(REP_DIR)/recipes/src/base-hw_content.inc
|
||||
1
recipes/src/base-hw-odroid_xu/hash
Normal file
1
recipes/src/base-hw-odroid_xu/hash
Normal file
@@ -0,0 +1 @@
|
||||
2020-04-08 a6f0c5c419530587e8b5c8c0b1e8e815ea82bde6
|
||||
2
recipes/src/base-hw-odroid_xu/used_apis
Normal file
2
recipes/src/base-hw-odroid_xu/used_apis
Normal file
@@ -0,0 +1,2 @@
|
||||
base-hw
|
||||
base
|
||||
28
src/bootstrap/spec/arndale/board.h
Normal file
28
src/bootstrap/spec/arndale/board.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* \brief Arndale specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-04-03
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
|
||||
|
||||
#include <hw/spec/arm/arndale_board.h>
|
||||
#include <hw/spec/arm/lpae.h>
|
||||
#include <spec/arm/cpu.h>
|
||||
#include <hw/spec/arm/gicv2.h>
|
||||
|
||||
namespace Board {
|
||||
using namespace Hw::Arndale_board;
|
||||
using Pic = Hw::Gicv2;
|
||||
static constexpr bool NON_SECURE = true;
|
||||
}
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_ */
|
||||
25
src/bootstrap/spec/arndale/cpu.cc
Normal file
25
src/bootstrap/spec/arndale/cpu.cc
Normal file
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* \brief CPU-specific initialization code for Arndale
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2016-01-07
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2016-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* core includes */
|
||||
#include <cpu.h>
|
||||
#include <translation_table.h>
|
||||
|
||||
|
||||
|
||||
void Genode::Cpu::init(Genode::Translation_table & table)
|
||||
{
|
||||
prepare_nonsecure_world();
|
||||
prepare_hypervisor(table);
|
||||
switch_to_supervisor_mode();
|
||||
}
|
||||
84
src/bootstrap/spec/arndale/platform.cc
Normal file
84
src/bootstrap/spec/arndale/platform.cc
Normal file
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* \brief Parts of platform that are specific to Arndale
|
||||
* \author Martin Stein
|
||||
* \date 2012-04-27
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <spec/arm/cortex_a7_a15_virtualization.h>
|
||||
#include <platform.h>
|
||||
|
||||
extern "C" void * _start_setup_stack; /* entrypoint for non-boot CPUs */
|
||||
static unsigned char hyp_mode_stack[1024]; /* hypervisor mode's kernel stack */
|
||||
|
||||
using namespace Board;
|
||||
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
|
||||
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
|
||||
Memory_region { MCT_MMIO_BASE, MCT_MMIO_SIZE },
|
||||
Memory_region { UART_2_MMIO_BASE, UART_2_MMIO_SIZE }) { }
|
||||
|
||||
|
||||
static inline void switch_to_supervisor_mode()
|
||||
{
|
||||
using Cpsr = Hw::Arm_cpu::Psr;
|
||||
|
||||
Cpsr::access_t cpsr = 0;
|
||||
Cpsr::M::set(cpsr, Cpsr::M::SVC);
|
||||
Cpsr::F::set(cpsr, 1);
|
||||
Cpsr::I::set(cpsr, 1);
|
||||
|
||||
asm volatile (
|
||||
"msr sp_svc, sp \n" /* copy current mode's sp */
|
||||
"msr lr_svc, lr \n" /* copy current mode's lr */
|
||||
"msr elr_hyp, lr \n" /* copy current mode's lr to hyp lr */
|
||||
"msr sp_hyp, %[stack] \n" /* copy to hyp stack pointer */
|
||||
"msr spsr_cxfs, %[cpsr] \n" /* set psr for supervisor mode */
|
||||
"adr lr, 1f \n" /* load exception return address */
|
||||
"eret \n" /* exception return */
|
||||
"1:":: [cpsr] "r" (cpsr), [stack] "r" (&hyp_mode_stack));
|
||||
}
|
||||
|
||||
|
||||
unsigned Bootstrap::Platform::enable_mmu()
|
||||
{
|
||||
static volatile bool primary_cpu = true;
|
||||
static unsigned long timer_freq = 24000000;
|
||||
|
||||
/* locally initialize interrupt controller */
|
||||
::Board::Pic pic { };
|
||||
|
||||
volatile unsigned long * mct_control = (unsigned long*) 0x101C0240;
|
||||
*mct_control = 0x100;
|
||||
prepare_nonsecure_world(timer_freq);
|
||||
prepare_hypervisor((addr_t)core_pd->table_base);
|
||||
switch_to_supervisor_mode();
|
||||
|
||||
Cpu::Sctlr::init();
|
||||
Cpu::Cpsr::init();
|
||||
|
||||
/* primary cpu wakes up all others */
|
||||
if (primary_cpu && NR_OF_CPUS > 1) {
|
||||
Cpu::invalidate_data_cache();
|
||||
primary_cpu = false;
|
||||
Cpu::wake_up_all_cpus(&_start_setup_stack);
|
||||
}
|
||||
|
||||
Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
|
||||
|
||||
return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
|
||||
}
|
||||
|
||||
|
||||
void Board::Cpu::wake_up_all_cpus(void * const ip)
|
||||
{
|
||||
*(void * volatile *)Board::IRAM_BASE = ip;
|
||||
asm volatile("dsb; sev;");
|
||||
}
|
||||
28
src/bootstrap/spec/odroid_xu/board.h
Normal file
28
src/bootstrap/spec/odroid_xu/board.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* \brief Odroid XU specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-04-03
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
|
||||
|
||||
#include <hw/spec/arm/odroid_xu_board.h>
|
||||
#include <hw/spec/arm/lpae.h>
|
||||
#include <spec/arm/cpu.h>
|
||||
#include <hw/spec/arm/gicv2.h>
|
||||
|
||||
namespace Board {
|
||||
using namespace Hw::Odroid_xu_board;
|
||||
using Pic = Hw::Gicv2;
|
||||
static constexpr bool NON_SECURE = false;
|
||||
}
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_ */
|
||||
36
src/bootstrap/spec/odroid_xu/platform.cc
Normal file
36
src/bootstrap/spec/odroid_xu/platform.cc
Normal file
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* \brief Parts of platform that are specific to Odroid XU
|
||||
* \author Martin Stein
|
||||
* \date 2012-04-27
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <platform.h>
|
||||
|
||||
using namespace Board;
|
||||
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
|
||||
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
|
||||
Memory_region { IRQ_CONTROLLER_VT_CTRL_BASE, IRQ_CONTROLLER_VT_CTRL_SIZE },
|
||||
Memory_region { MCT_MMIO_BASE, MCT_MMIO_SIZE },
|
||||
Memory_region { UART_2_MMIO_BASE, UART_2_MMIO_SIZE }) { }
|
||||
|
||||
|
||||
unsigned Bootstrap::Platform::enable_mmu()
|
||||
{
|
||||
/* locally initialize interrupt controller */
|
||||
::Board::Pic pic { };
|
||||
|
||||
Cpu::Sctlr::init();
|
||||
Cpu::Cpsr::init();
|
||||
Cpu::invalidate_data_cache();
|
||||
Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
|
||||
return 0;
|
||||
}
|
||||
97
src/core/spec/arm/exynos_mct.cc
Normal file
97
src/core/spec/arm/exynos_mct.cc
Normal file
@@ -0,0 +1,97 @@
|
||||
/*
|
||||
* \brief Timer driver for core
|
||||
* \author Stefan Kalkowski
|
||||
* \author Martin stein
|
||||
* \date 2013-01-10
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* core include */
|
||||
#include <kernel/timer.h>
|
||||
#include <board.h>
|
||||
#include <platform.h>
|
||||
|
||||
#include <drivers/timer/util.h>
|
||||
|
||||
using namespace Genode;
|
||||
using namespace Kernel;
|
||||
|
||||
|
||||
unsigned Timer::interrupt_id() const
|
||||
{
|
||||
switch (_device.cpu_id) {
|
||||
case 0: return Board::MCT_IRQ_L0;
|
||||
case 1: return Board::MCT_IRQ_L1;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Board::Timer::Timer(unsigned cpu_id)
|
||||
:
|
||||
Mmio(Platform::mmio_to_virt(Board::MCT_MMIO_BASE)),
|
||||
local(Platform::mmio_to_virt(Board::MCT_MMIO_BASE)
|
||||
+ (cpu_id ? L1 : L0)),
|
||||
ticks_per_ms(calc_ticks_per_ms(Board::MCT_CLOCK)),
|
||||
cpu_id(cpu_id)
|
||||
{
|
||||
static unsigned initialized = 0;
|
||||
if (initialized++) return;
|
||||
|
||||
Mct_cfg::access_t mct_cfg = 0;
|
||||
Mct_cfg::Prescaler::set(mct_cfg, PRESCALER);
|
||||
Mct_cfg::Div_mux::set(mct_cfg, DIV_MUX);
|
||||
write<Mct_cfg>(mct_cfg);
|
||||
}
|
||||
|
||||
|
||||
Board::Timer::Local::Local(Genode::addr_t base)
|
||||
: Mmio(base)
|
||||
{
|
||||
write<Int_enb>(Int_enb::Frceie::bits(1));
|
||||
|
||||
acked_write<Tcntb, Wstat::Tcntb>(0xffffffff);
|
||||
acked_write<Frcntb, Wstat::Frcntb>(0xffffffff);
|
||||
|
||||
Tcon::access_t tcon = 0;
|
||||
Tcon::Frc_start::set(tcon, 1);
|
||||
Tcon::Timer_start::set(tcon, 1);
|
||||
acked_write<Tcon, Wstat::Tcon>(tcon);
|
||||
}
|
||||
|
||||
|
||||
void Timer::_start_one_shot(time_t const ticks)
|
||||
{
|
||||
using Device = Board::Timer;
|
||||
_device.local.cnt = _device.local.read<Device::Local::Tcnto>();
|
||||
_device.local.write<Device::Local::Int_cstat::Frccnt>(1);
|
||||
_device.local.acked_write<Device::Local::Frcntb,
|
||||
Device::Local::Wstat::Frcntb>(ticks);
|
||||
}
|
||||
|
||||
|
||||
time_t Timer::_duration() const
|
||||
{
|
||||
using Tcnto = Board::Timer::Local::Tcnto;
|
||||
unsigned long ret = _device.local.cnt - _device.local.read<Tcnto>();
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
|
||||
time_t Timer::ticks_to_us(time_t const ticks) const {
|
||||
return timer_ticks_to_us(ticks, _device.ticks_per_ms); }
|
||||
|
||||
|
||||
time_t Timer::us_to_ticks(time_t const us) const {
|
||||
return (us / 1000) * _device.ticks_per_ms; }
|
||||
|
||||
|
||||
time_t Timer::_max_value() const {
|
||||
return 0xffffffff; }
|
||||
121
src/core/spec/arm/exynos_mct.h
Normal file
121
src/core/spec/arm/exynos_mct.h
Normal file
@@ -0,0 +1,121 @@
|
||||
/*
|
||||
* \brief Timer driver for core
|
||||
* \author Martin stein
|
||||
* \date 2013-01-10
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Kernel OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__CORE__SPEC__ARM__EXYNOS_MCT_H_
|
||||
#define _SRC__CORE__SPEC__ARM__EXYNOS_MCT_H_
|
||||
|
||||
/* Kernel includes */
|
||||
#include <util/mmio.h>
|
||||
|
||||
/* base-hw includes */
|
||||
#include <kernel/types.h>
|
||||
|
||||
namespace Board { class Timer; }
|
||||
|
||||
|
||||
struct Board::Timer : Genode::Mmio
|
||||
{
|
||||
enum {
|
||||
PRESCALER = 1,
|
||||
DIV_MUX = 0,
|
||||
};
|
||||
|
||||
/**
|
||||
* MCT configuration
|
||||
*/
|
||||
struct Mct_cfg : Register<0x0, 32>
|
||||
{
|
||||
struct Prescaler : Bitfield<0, 8> { };
|
||||
struct Div_mux : Bitfield<8, 3> { };
|
||||
};
|
||||
|
||||
|
||||
/*****************
|
||||
** Local timer **
|
||||
*****************/
|
||||
|
||||
enum Local_timer_offset { L0 = 0x300, L1 = 0x400 };
|
||||
|
||||
struct Local : Genode::Mmio {
|
||||
|
||||
struct Tcntb : Register<0x0, 32> { };
|
||||
struct Tcnto : Register<0x4, 32> { };
|
||||
struct Icntb : Register<0x8, 32> { };
|
||||
struct Icnto : Register<0xc, 32> { };
|
||||
struct Frcntb : Register<0x10, 32> { };
|
||||
struct Frcnto : Register<0x14, 32> { };
|
||||
|
||||
struct Tcon : Register<0x20, 32>
|
||||
{
|
||||
struct Timer_start : Bitfield<0, 1> { };
|
||||
struct Irq_start : Bitfield<1, 1> { };
|
||||
struct Irq_type : Bitfield<2, 1> { };
|
||||
struct Frc_start : Bitfield<3, 1> { };
|
||||
};
|
||||
|
||||
struct Int_cstat : Register<0x30, 32, true>
|
||||
{
|
||||
struct Intcnt : Bitfield<0, 1> { };
|
||||
struct Frccnt : Bitfield<1, 1> { };
|
||||
};
|
||||
|
||||
struct Int_enb : Register<0x34, 32>
|
||||
{
|
||||
struct Inteie : Bitfield<0, 1> { };
|
||||
struct Frceie : Bitfield<1, 1> { };
|
||||
};
|
||||
|
||||
struct Wstat : Register<0x40, 32, true>
|
||||
{
|
||||
struct Tcntb : Bitfield<0, 1> { };
|
||||
struct Icntb : Bitfield<1, 1> { };
|
||||
struct Frcntb : Bitfield<2, 1> { };
|
||||
struct Tcon : Bitfield<3, 1> { };
|
||||
};
|
||||
|
||||
Tcnto::access_t cnt = { 0 };
|
||||
|
||||
/**
|
||||
* Write to reg that replies via ack bit and clear ack bit
|
||||
*/
|
||||
template <typename DEST, typename ACK>
|
||||
void acked_write(typename DEST::Register_base::access_t const v)
|
||||
{
|
||||
typedef typename DEST::Register_base Dest;
|
||||
typedef typename ACK::Bitfield_base Ack;
|
||||
write<Dest>(v);
|
||||
while (!read<Ack>());
|
||||
write<Ack>(1);
|
||||
}
|
||||
|
||||
void update_cnt() { cnt = read<Tcnto>(); }
|
||||
|
||||
Local(Genode::addr_t base);
|
||||
};
|
||||
|
||||
/**
|
||||
* Calculate amount of ticks per ms for specific input clock
|
||||
*
|
||||
* \param clock input clock
|
||||
*/
|
||||
Kernel::time_t static calc_ticks_per_ms(unsigned const clock) {
|
||||
return clock / (PRESCALER + 1) / (1 << DIV_MUX) / 1000; }
|
||||
|
||||
Local local;
|
||||
unsigned const ticks_per_ms;
|
||||
unsigned const cpu_id;
|
||||
|
||||
Timer(unsigned cpu_id);
|
||||
};
|
||||
|
||||
#endif /* _SRC__CORE__SPEC__ARM__EXYNOS_MCT_H_ */
|
||||
33
src/core/spec/arndale/board.h
Normal file
33
src/core/spec/arndale/board.h
Normal file
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* \brief Board driver for core
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-04-27
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _CORE__SPEC__ARNDALE__BOARD_H_
|
||||
#define _CORE__SPEC__ARNDALE__BOARD_H_
|
||||
|
||||
#include <spec/arm/virtualization/gicv2.h>
|
||||
#include <hw/spec/arm/arndale_board.h>
|
||||
#include <spec/arm/exynos_mct.h>
|
||||
#include <spec/arm/cpu/vm_state_virtualization.h>
|
||||
#include <spec/arm/virtualization/board.h>
|
||||
|
||||
namespace Kernel { class Cpu; }
|
||||
|
||||
namespace Board {
|
||||
using namespace Hw::Arndale_board;
|
||||
|
||||
struct Virtual_local_pic {};
|
||||
|
||||
enum { VCPU_MAX = 1 };
|
||||
}
|
||||
|
||||
#endif /* _CORE__SPEC__ARNDALE__BOARD_H_ */
|
||||
27
src/core/spec/odroid_xu/board.h
Normal file
27
src/core/spec/odroid_xu/board.h
Normal file
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* \brief Board driver for core
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-04-27
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _CORE__SPEC__ODROID_XU__BOARD_H_
|
||||
#define _CORE__SPEC__ODROID_XU__BOARD_H_
|
||||
|
||||
#include <hw/spec/arm/gicv2.h>
|
||||
#include <hw/spec/arm/odroid_xu_board.h>
|
||||
#include <spec/arm/exynos_mct.h>
|
||||
|
||||
namespace Board {
|
||||
using namespace Hw::Odroid_xu_board;
|
||||
|
||||
using Pic = Hw::Gicv2;
|
||||
}
|
||||
|
||||
#endif /* _CORE__SPEC__ODROID_XU__BOARD_H_ */
|
||||
1113
src/drivers/framebuffer/spec/exynos5/driver.cc
Normal file
1113
src/drivers/framebuffer/spec/exynos5/driver.cc
Normal file
File diff suppressed because it is too large
Load Diff
108
src/drivers/framebuffer/spec/exynos5/driver.h
Normal file
108
src/drivers/framebuffer/spec/exynos5/driver.h
Normal file
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* \brief Framebuffer driver for Exynos5 HDMI
|
||||
* \author Martin Stein
|
||||
* \date 2013-08-09
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _DRIVER_H_
|
||||
#define _DRIVER_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <base/component.h>
|
||||
#include <base/stdint.h>
|
||||
#include <base/log.h>
|
||||
|
||||
namespace Framebuffer
|
||||
{
|
||||
using namespace Genode;
|
||||
|
||||
/**
|
||||
* Framebuffer driver
|
||||
*/
|
||||
class Driver;
|
||||
}
|
||||
|
||||
class Framebuffer::Driver
|
||||
{
|
||||
public:
|
||||
|
||||
enum Format { FORMAT_RGB565 };
|
||||
enum Output { OUTPUT_LCD, OUTPUT_HDMI };
|
||||
|
||||
private:
|
||||
|
||||
Genode::Env &_env;
|
||||
|
||||
size_t _fb_width;
|
||||
size_t _fb_height;
|
||||
Format _fb_format;
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Constructor
|
||||
*/
|
||||
Driver(Genode::Env &env)
|
||||
:
|
||||
_env(env),
|
||||
_fb_width(0),
|
||||
_fb_height(0),
|
||||
_fb_format(FORMAT_RGB565)
|
||||
{ }
|
||||
|
||||
/**
|
||||
* Return amount of bytes that is used for one pixel descriptor
|
||||
*
|
||||
* \param format pixel format
|
||||
*
|
||||
* \retval 0 failed
|
||||
* \retval >0 succeeded
|
||||
*/
|
||||
static size_t bytes_per_pixel(Format format)
|
||||
{
|
||||
switch (format) {
|
||||
case FORMAT_RGB565:
|
||||
return 2;
|
||||
default:
|
||||
error("unknown pixel format");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Return size of framebuffer in bytes
|
||||
*
|
||||
* \param width width of framebuffer in pixel
|
||||
* \param height height of framebuffer in pixel
|
||||
* \param format pixel format of framebuffer
|
||||
*
|
||||
* \retval 0 failed
|
||||
* \retval >0 succeeded
|
||||
*/
|
||||
size_t buffer_size(size_t width, size_t height, Format format)
|
||||
{
|
||||
return bytes_per_pixel(format) * width * height;
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize driver for HDMI output
|
||||
*
|
||||
* \param width width of screen and framebuffer in pixel
|
||||
* \param height height of screen and framebuffer in pixel
|
||||
* \param format pixel format of framebuffer
|
||||
* \param fb_phys physical base of framebuffer
|
||||
*
|
||||
* \retval -1 failed
|
||||
* \retval 0 succeeded
|
||||
*/
|
||||
int init(size_t width, size_t height, Format format, addr_t fb_phys);
|
||||
};
|
||||
|
||||
#endif /* _DRIVER_H_ */
|
||||
147
src/drivers/framebuffer/spec/exynos5/main.cc
Normal file
147
src/drivers/framebuffer/spec/exynos5/main.cc
Normal file
@@ -0,0 +1,147 @@
|
||||
/*
|
||||
* \brief Framebuffer driver for Exynos5 HDMI
|
||||
* \author Martin Stein
|
||||
* \date 2013-08-09
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* Genode includes */
|
||||
#include <base/attached_rom_dataspace.h>
|
||||
#include <base/component.h>
|
||||
#include <framebuffer_session/framebuffer_session.h>
|
||||
#include <timer_session/connection.h>
|
||||
#include <dataspace/client.h>
|
||||
#include <base/log.h>
|
||||
#include <os/static_root.h>
|
||||
#include <util/string.h>
|
||||
|
||||
/* local includes */
|
||||
#include <driver.h>
|
||||
|
||||
namespace Framebuffer
|
||||
{
|
||||
using namespace Genode;
|
||||
|
||||
/**
|
||||
* Framebuffer session backend
|
||||
*/
|
||||
class Session_component;
|
||||
struct Main;
|
||||
};
|
||||
|
||||
class Framebuffer::Session_component
|
||||
:
|
||||
public Genode::Rpc_object<Framebuffer::Session>
|
||||
{
|
||||
private:
|
||||
|
||||
Genode::Env &_env;
|
||||
|
||||
unsigned _width;
|
||||
unsigned _height;
|
||||
Driver::Format _format;
|
||||
size_t _size;
|
||||
Dataspace_capability _ds;
|
||||
addr_t _phys_base;
|
||||
Timer::Connection _timer { _env };
|
||||
|
||||
/**
|
||||
* Convert Driver::Format to Framebuffer::Mode::Format
|
||||
*/
|
||||
static Mode::Format _convert_format(Driver::Format driver_format)
|
||||
{
|
||||
switch (driver_format) {
|
||||
case Driver::FORMAT_RGB565: return Mode::RGB565;
|
||||
}
|
||||
return Mode::INVALID;
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Constructor
|
||||
*
|
||||
* \param driver driver backend that communicates with hardware
|
||||
* \param width width of framebuffer in pixel
|
||||
* \param height height of framebuffer in pixel
|
||||
* \param output targeted output device
|
||||
*/
|
||||
Session_component(Genode::Env &env, Driver &driver,
|
||||
unsigned width, unsigned height)
|
||||
:
|
||||
_env(env),
|
||||
_width(width),
|
||||
_height(height),
|
||||
_format(Driver::FORMAT_RGB565),
|
||||
_size(driver.buffer_size(width, height, _format)),
|
||||
_ds(_env.ram().alloc(_size, WRITE_COMBINED)),
|
||||
_phys_base(Dataspace_client(_ds).phys_addr())
|
||||
{
|
||||
if (driver.init(width, height, _format, _phys_base)) {
|
||||
error("could not initialize display");
|
||||
struct Could_not_initialize_display : Exception { };
|
||||
throw Could_not_initialize_display();
|
||||
}
|
||||
}
|
||||
|
||||
/************************************
|
||||
** Framebuffer::Session interface **
|
||||
************************************/
|
||||
|
||||
Dataspace_capability dataspace() override { return _ds; }
|
||||
|
||||
Mode mode() const override
|
||||
{
|
||||
return Mode(_width, _height, _convert_format(_format));
|
||||
}
|
||||
|
||||
void mode_sigh(Genode::Signal_context_capability) override { }
|
||||
|
||||
void sync_sigh(Genode::Signal_context_capability sigh) override
|
||||
{
|
||||
_timer.sigh(sigh);
|
||||
_timer.trigger_periodic(10*1000);
|
||||
}
|
||||
|
||||
void refresh(int, int, int, int) override { }
|
||||
};
|
||||
|
||||
|
||||
static unsigned config_dimension(Genode::Xml_node node, char const *attr,
|
||||
unsigned default_value)
|
||||
{
|
||||
return node.attribute_value(attr, default_value);
|
||||
}
|
||||
|
||||
|
||||
struct Main
|
||||
{
|
||||
Genode::Env &_env;
|
||||
Genode::Entrypoint &_ep;
|
||||
|
||||
Genode::Attached_rom_dataspace _config { _env, "config" };
|
||||
|
||||
Framebuffer::Driver _driver { _env };
|
||||
|
||||
Framebuffer::Session_component _fb_session { _env, _driver,
|
||||
config_dimension(_config.xml(), "width", 1920),
|
||||
config_dimension(_config.xml(), "height", 1080)
|
||||
};
|
||||
|
||||
Genode::Static_root<Framebuffer::Session> _fb_root { _ep.manage(_fb_session) };
|
||||
|
||||
Main(Genode::Env &env) : _env(env), _ep(_env.ep())
|
||||
{
|
||||
/* announce service and relax */
|
||||
_env.parent().announce(_ep.manage(_fb_root));
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
void Component::construct(Genode::Env &env) { static Main main(env); }
|
||||
8
src/drivers/framebuffer/spec/exynos5/target.mk
Normal file
8
src/drivers/framebuffer/spec/exynos5/target.mk
Normal file
@@ -0,0 +1,8 @@
|
||||
TARGET = exynos5_fb_drv
|
||||
REQUIRES = arm_v7
|
||||
SRC_CC += main.cc driver.cc
|
||||
LIBS += base
|
||||
INC_DIR += $(PRG_DIR)
|
||||
INC_DIR += $(call select_from_repositories,include/spec/exynos5)
|
||||
|
||||
CC_CXX_WARN_STRICT :=
|
||||
545
src/drivers/platform/spec/arndale/cmu.h
Normal file
545
src/drivers/platform/spec/arndale/cmu.h
Normal file
@@ -0,0 +1,545 @@
|
||||
/*
|
||||
* \brief Regulator driver for clock management unit of Exynos5250 SoC
|
||||
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
|
||||
* \date 2013-06-13
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _DRIVERS__PLATFORM__SPEC__ARNDALE__CMU_H_
|
||||
#define _DRIVERS__PLATFORM__SPEC__ARNDALE__CMU_H_
|
||||
|
||||
#include <base/log.h>
|
||||
#include <regulator/consts.h>
|
||||
#include <regulator/driver.h>
|
||||
#include <os/attached_mmio.h>
|
||||
|
||||
using namespace Regulator;
|
||||
using Genode::warning;
|
||||
|
||||
class Cmu : public Regulator::Driver,
|
||||
private Genode::Attached_mmio
|
||||
{
|
||||
private:
|
||||
|
||||
enum {
|
||||
CMU_MMIO_BASE = 0x10010000,
|
||||
CMU_MMIO_SIZE = 0x24000,
|
||||
};
|
||||
|
||||
static const Genode::uint16_t m_values[]; /* M values for frequencies */
|
||||
static const Genode::uint8_t p_values[]; /* P values for frequencies */
|
||||
static const Genode::uint8_t s_values[]; /* S values for frequencies */
|
||||
|
||||
template <unsigned OFF>
|
||||
struct Pll_lock : Register<OFF, 32>
|
||||
{
|
||||
struct Pll_locktime : Register<OFF, 32>::template Bitfield<0, 20> { };
|
||||
|
||||
static Genode::uint32_t max_lock_time(Genode::uint8_t pdiv) {
|
||||
return pdiv * 250; };
|
||||
};
|
||||
|
||||
template <unsigned OFF>
|
||||
struct Pll_con0 : Register<OFF, 32>
|
||||
{
|
||||
struct S : Register<OFF, 32>::template Bitfield < 0, 3> { };
|
||||
struct P : Register<OFF, 32>::template Bitfield < 8, 6> { };
|
||||
struct M : Register<OFF, 32>::template Bitfield <16, 10> { };
|
||||
struct Locked : Register<OFF, 32>::template Bitfield <29, 1> { };
|
||||
struct Enable : Register<OFF, 32>::template Bitfield <31, 1> { };
|
||||
};
|
||||
|
||||
|
||||
/***********************
|
||||
** CMU CPU registers **
|
||||
***********************/
|
||||
|
||||
typedef Pll_lock<0> Apll_lock;
|
||||
typedef Pll_con0<0x100> Apll_con0;
|
||||
|
||||
struct Clk_src_cpu : Register<0x200, 32>
|
||||
{
|
||||
struct Mux_cpu_sel : Bitfield<16, 1>
|
||||
{
|
||||
enum { MOUT_APLL, SCLK_MPLL};
|
||||
};
|
||||
};
|
||||
|
||||
struct Clk_mux_stat_cpu : Register<0x400, 32>
|
||||
{
|
||||
struct Cpu_sel : Bitfield<16, 3>
|
||||
{
|
||||
enum { MOUT_APLL = 0b1, SCLK_MPLL = 0b10 };
|
||||
};
|
||||
};
|
||||
|
||||
struct Clk_div_cpu0 : Register<0x500, 32>
|
||||
{
|
||||
/* Cpu0 divider values for frequencies 200 - 1700 */
|
||||
static const Genode::uint32_t values[];
|
||||
};
|
||||
|
||||
struct Clk_div_cpu1 : Register<0x504, 32>
|
||||
{
|
||||
/* Divider for cpu1 doesn't change */
|
||||
enum { FIX_VALUE = 32 };
|
||||
};
|
||||
|
||||
struct Clk_div_stat_cpu0 : Register<0x600, 32>
|
||||
{
|
||||
struct Div_arm : Bitfield< 0, 1> {};
|
||||
struct Div_cpud : Bitfield< 4, 1> {};
|
||||
struct Div_acp : Bitfield< 8, 1> {};
|
||||
struct Div_pheriph : Bitfield<12, 1> {};
|
||||
struct Div_atb : Bitfield<16, 1> {};
|
||||
struct Div_pclk_dbg : Bitfield<20, 1> {};
|
||||
struct Div_apll : Bitfield<24, 1> {};
|
||||
struct Div_arm2 : Bitfield<28, 1> {};
|
||||
|
||||
static bool in_progress(access_t stat_word)
|
||||
{
|
||||
return stat_word & (Div_arm::bits(1) |
|
||||
Div_cpud::bits(1) |
|
||||
Div_acp::bits(1) |
|
||||
Div_pheriph::bits(1) |
|
||||
Div_atb::bits(1) |
|
||||
Div_pclk_dbg::bits(1) |
|
||||
Div_apll::bits(1) |
|
||||
Div_arm2::bits(1));
|
||||
}
|
||||
};
|
||||
|
||||
struct Clk_div_stat_cpu1 : Register<0x604, 32>
|
||||
{
|
||||
struct Div_copy : Bitfield<0, 1> { };
|
||||
struct Div_hpm : Bitfield<4, 1> { };
|
||||
|
||||
static bool in_progress(access_t stat_word)
|
||||
{
|
||||
return stat_word & (Div_copy::bits(1) |
|
||||
Div_hpm::bits(1));
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
/************************
|
||||
** CMU CORE registers **
|
||||
************************/
|
||||
|
||||
typedef Pll_lock<0x4000> Mpll_lock;
|
||||
typedef Pll_con0<0x4100> Mpll_con0;
|
||||
|
||||
struct Clk_src_core1 : Register<0x4204, 32>
|
||||
{
|
||||
struct Mux_mpll_sel : Bitfield<8, 1> { enum { XXTI, MPLL_FOUT_RGT }; };
|
||||
};
|
||||
|
||||
struct Clk_gate_ip_acp : Register<0x8800, 32> { };
|
||||
struct Clk_gate_ip_isp0 : Register<0xc800, 32> { };
|
||||
struct Clk_gate_ip_isp1 : Register<0xc804, 32> { };
|
||||
struct Clk_gate_sclk_isp : Register<0xc900, 32> { };
|
||||
|
||||
|
||||
/***********************
|
||||
** CMU TOP registers **
|
||||
***********************/
|
||||
|
||||
typedef Pll_lock<0x10020> Cpll_lock;
|
||||
typedef Pll_lock<0x10030> Epll_lock;
|
||||
typedef Pll_lock<0x10040> Vpll_lock;
|
||||
typedef Pll_lock<0x10050> Gpll_lock;
|
||||
typedef Pll_con0<0x10120> Cpll_con0;
|
||||
typedef Pll_con0<0x10130> Epll_con0;
|
||||
typedef Pll_con0<0x10140> Vpll_con0;
|
||||
typedef Pll_con0<0x10150> Gpll_con0;
|
||||
|
||||
struct Clk_src_top2 : Register<0x10218, 32>
|
||||
{
|
||||
struct Mux_mpll_user_sel : Bitfield<20, 1> { enum { XXTI, MOUT_MPLL}; };
|
||||
};
|
||||
|
||||
struct Clk_src_fsys : Register<0x10244, 32>
|
||||
{
|
||||
struct Sata_sel : Bitfield<24, 1> {
|
||||
enum { SCLK_MPLL_USER, SCLK_BPLL_USER }; };
|
||||
struct Usbdrd30_sel : Bitfield<28, 1> {
|
||||
enum { SCLK_MPLL_USER, SCLK_CPLL }; };
|
||||
};
|
||||
|
||||
struct Clk_src_mask_fsys : Register<0x10340, 32>
|
||||
{
|
||||
struct Mmc0_mask : Bitfield<0, 1> { enum { MASK, UNMASK }; };
|
||||
struct Sata_mask : Bitfield<24, 1> { enum { MASK, UNMASK }; };
|
||||
struct Usbdrd30_mask : Bitfield<28, 1> { enum { MASK, UNMASK }; };
|
||||
};
|
||||
|
||||
struct Clk_div_fsys0 : Register<0x10548, 32>
|
||||
{
|
||||
struct Sata_ratio : Bitfield<20, 4> { };
|
||||
struct Usbdrd30_ratio : Bitfield<24, 4> { };
|
||||
};
|
||||
|
||||
struct Clk_div_stat_fsys0 : Register<0x10648, 32>
|
||||
{
|
||||
struct Div_sata : Bitfield<20, 1> {};
|
||||
struct Div_usbdrd30 : Bitfield<24, 1> {};
|
||||
};
|
||||
|
||||
struct Clk_gate_ip_gscl : Register<0x10920, 32> { };
|
||||
struct Clk_gate_ip_disp1 : Register<0x10928, 32>
|
||||
{
|
||||
struct Clk_mixer : Bitfield<5, 1> { };
|
||||
struct Clk_hdmi : Bitfield<6, 1> { };
|
||||
};
|
||||
struct Clk_gate_ip_mfc : Register<0x1092c, 32> { };
|
||||
struct Clk_gate_ip_g3d : Register<0x10930, 32> { };
|
||||
struct Clk_gate_ip_gen : Register<0x10934, 32> { };
|
||||
|
||||
struct Clk_gate_ip_fsys : Register<0x10944, 32>
|
||||
{
|
||||
struct Pdma0 : Bitfield<1, 1> { };
|
||||
struct Pdma1 : Bitfield<2, 1> { };
|
||||
struct Sata : Bitfield<6, 1> { };
|
||||
struct Sdmmc0 : Bitfield<12, 1> { };
|
||||
struct Usbhost20 : Bitfield<18, 1> { };
|
||||
struct Usbdrd30 : Bitfield<19, 1> { };
|
||||
struct Sata_phy_ctrl : Bitfield<24, 1> { };
|
||||
struct Sata_phy_i2c : Bitfield<25, 1> { };
|
||||
};
|
||||
|
||||
struct Clk_src_disp1_0 : Register<0x1022c, 32>
|
||||
{
|
||||
struct Hdmi_sel : Bitfield<20, 1> { };
|
||||
};
|
||||
|
||||
struct Clk_src_mask_disp1_0 : Register<0x1032c, 32>
|
||||
{
|
||||
struct Hdmi_mask : Bitfield<20, 1> { };
|
||||
};
|
||||
|
||||
struct Clk_gate_ip_peric : Register<0x10950, 32>
|
||||
{
|
||||
struct Clk_uart2 : Bitfield<2, 1> { };
|
||||
struct Clk_i2chdmi : Bitfield<14, 1> { };
|
||||
struct Clk_pwm : Bitfield<24, 1> { };
|
||||
};
|
||||
|
||||
struct Clk_gate_block : Register<0x10980, 32>
|
||||
{
|
||||
struct Clk_disp1 : Bitfield<5, 1> { };
|
||||
struct Clk_gen : Bitfield<2, 1> { };
|
||||
};
|
||||
|
||||
|
||||
/*************************
|
||||
** CMU CDREX registers **
|
||||
*************************/
|
||||
|
||||
typedef Pll_lock<0x20010> Bpll_lock;
|
||||
typedef Pll_con0<0x20110> Bpll_con0;
|
||||
|
||||
struct Pll_div2_sel : Register<0x20a24, 32>
|
||||
{
|
||||
struct Mpll_fout_sel : Bitfield<4, 1> {
|
||||
enum { MPLL_FOUT_HALF, MPLL_FOUT }; };
|
||||
};
|
||||
|
||||
|
||||
/*******************
|
||||
** CPU functions **
|
||||
*******************/
|
||||
|
||||
Cpu_clock_freq _cpu_freq;
|
||||
|
||||
void _cpu_clk_freq(unsigned long level)
|
||||
{
|
||||
unsigned freq;
|
||||
switch (level) {
|
||||
case CPU_FREQ_200:
|
||||
freq = 0;
|
||||
break;
|
||||
case CPU_FREQ_400:
|
||||
freq = 1;
|
||||
break;
|
||||
case CPU_FREQ_600:
|
||||
freq = 2;
|
||||
break;
|
||||
case CPU_FREQ_800:
|
||||
freq = 3;
|
||||
break;
|
||||
case CPU_FREQ_1000:
|
||||
freq = 4;
|
||||
break;
|
||||
case CPU_FREQ_1200:
|
||||
freq = 5;
|
||||
break;
|
||||
case CPU_FREQ_1400:
|
||||
freq = 6;
|
||||
break;
|
||||
case CPU_FREQ_1600:
|
||||
freq = 7;
|
||||
break;
|
||||
case CPU_FREQ_1700:
|
||||
freq = 8;
|
||||
break;
|
||||
default:
|
||||
warning("Unsupported CPU frequency level ", level);
|
||||
warning("Supported values are 200, 400, 600, 800 MHz");
|
||||
warning("and 1, 1.2, 1.4, 1.6, 1.7 GHz");
|
||||
return;
|
||||
};
|
||||
|
||||
/**
|
||||
* change clock divider values
|
||||
*/
|
||||
|
||||
/* cpu0 divider */
|
||||
write<Clk_div_cpu0>(Clk_div_cpu0::values[freq]);
|
||||
while (Clk_div_stat_cpu0::in_progress(read<Clk_div_stat_cpu0>())) ;
|
||||
|
||||
/* cpu1 divider */
|
||||
write<Clk_div_cpu1>(Clk_div_cpu1::FIX_VALUE);
|
||||
while (Clk_div_stat_cpu1::in_progress(read<Clk_div_stat_cpu1>())) ;
|
||||
|
||||
|
||||
/**
|
||||
* change APLL frequency
|
||||
*/
|
||||
|
||||
/* change reference clock to MPLL */
|
||||
write<Clk_src_cpu::Mux_cpu_sel>(Clk_src_cpu::Mux_cpu_sel::SCLK_MPLL);
|
||||
while (read<Clk_mux_stat_cpu::Cpu_sel>()
|
||||
!= Clk_mux_stat_cpu::Cpu_sel::SCLK_MPLL) ;
|
||||
|
||||
/* set lock time */
|
||||
unsigned pdiv = p_values[freq];
|
||||
write<Apll_lock::Pll_locktime>(Apll_lock::max_lock_time(pdiv));
|
||||
|
||||
/* change P, M, S values of APLL */
|
||||
write<Apll_con0::P>(p_values[freq]);
|
||||
write<Apll_con0::M>(m_values[freq]);
|
||||
write<Apll_con0::S>(s_values[freq]);
|
||||
|
||||
while (!read<Apll_con0::Locked>()) ;
|
||||
|
||||
/* change reference clock back to APLL */
|
||||
write<Clk_src_cpu::Mux_cpu_sel>(Clk_src_cpu::Mux_cpu_sel::MOUT_APLL);
|
||||
while (read<Clk_mux_stat_cpu::Cpu_sel>()
|
||||
!= Clk_mux_stat_cpu::Cpu_sel::MOUT_APLL) ;
|
||||
|
||||
_cpu_freq = static_cast<Cpu_clock_freq>(level);
|
||||
}
|
||||
|
||||
|
||||
/**********************
|
||||
** Device functions **
|
||||
**********************/
|
||||
|
||||
void _hdmi_enable()
|
||||
{
|
||||
write<Clk_gate_ip_peric::Clk_i2chdmi>(1);
|
||||
Clk_gate_ip_disp1::access_t gd1 = read<Clk_gate_ip_disp1>();
|
||||
Clk_gate_ip_disp1::Clk_mixer::set(gd1, 1);
|
||||
Clk_gate_ip_disp1::Clk_hdmi::set(gd1, 1);
|
||||
write<Clk_gate_ip_disp1>(gd1);
|
||||
write<Clk_gate_block::Clk_disp1>(1);
|
||||
write<Clk_src_mask_disp1_0::Hdmi_mask>(1);
|
||||
write<Clk_src_disp1_0::Hdmi_sel>(1);
|
||||
}
|
||||
|
||||
void _sata_enable()
|
||||
{
|
||||
/* enable I2C for SATA */
|
||||
write<Clk_gate_ip_fsys::Sata_phy_i2c>(1);
|
||||
|
||||
/**
|
||||
* set SATA clock to 66 MHz (nothing else supported)
|
||||
* assuming 800 MHz from sclk_mpll_user, formula: sclk / (divider + 1)
|
||||
*/
|
||||
write<Clk_div_fsys0::Sata_ratio>(11); /* */
|
||||
while (read<Clk_div_stat_fsys0::Div_sata>()) ;
|
||||
|
||||
/* enable SATA and SATA Phy */
|
||||
write<Clk_gate_ip_fsys::Sata>(1);
|
||||
write<Clk_gate_ip_fsys::Sata_phy_ctrl>(1);
|
||||
write<Clk_src_mask_fsys::Sata_mask>(1);
|
||||
}
|
||||
|
||||
void _usb30_enable()
|
||||
{
|
||||
/**
|
||||
* set USBDRD30 clock to 66 MHz
|
||||
* assuming 800 MHz from sclk_mpll_user, formula: sclk / (divider + 1)
|
||||
*/
|
||||
write<Clk_div_fsys0::Usbdrd30_ratio>(11);
|
||||
while (read<Clk_div_stat_fsys0::Div_usbdrd30>()) ;
|
||||
|
||||
/* enable USBDRD30 clock */
|
||||
write<Clk_gate_ip_fsys::Usbdrd30>(1);
|
||||
write<Clk_src_mask_fsys::Usbdrd30_mask>(1);
|
||||
}
|
||||
|
||||
void _enable(Regulator_id id)
|
||||
{
|
||||
switch (id) {
|
||||
case CLK_SATA:
|
||||
_sata_enable();
|
||||
break;
|
||||
case CLK_HDMI:
|
||||
_hdmi_enable();
|
||||
break;
|
||||
case CLK_USB30:
|
||||
_usb30_enable();
|
||||
break;
|
||||
case CLK_USB20:
|
||||
return write<Clk_gate_ip_fsys::Usbhost20>(1);
|
||||
case CLK_MMC0:
|
||||
write<Clk_gate_ip_fsys::Sdmmc0>(1);
|
||||
write<Clk_src_mask_fsys::Mmc0_mask>(1);
|
||||
break;
|
||||
default:
|
||||
warning("Unsupported for ", names[id].name);
|
||||
}
|
||||
}
|
||||
|
||||
void _disable(Regulator_id id)
|
||||
{
|
||||
switch (id) {
|
||||
case CLK_SATA:
|
||||
write<Clk_gate_ip_fsys::Sata_phy_i2c>(0);
|
||||
write<Clk_gate_ip_fsys::Sata>(0);
|
||||
write<Clk_gate_ip_fsys::Sata_phy_ctrl>(0);
|
||||
write<Clk_src_mask_fsys::Sata_mask>(0);
|
||||
break;
|
||||
case CLK_USB30:
|
||||
write<Clk_gate_ip_fsys::Usbdrd30>(0);
|
||||
write<Clk_src_mask_fsys::Usbdrd30_mask>(0);
|
||||
break;
|
||||
case CLK_USB20:
|
||||
return write<Clk_gate_ip_fsys::Usbhost20>(0);
|
||||
case CLK_MMC0:
|
||||
write<Clk_gate_ip_fsys::Sdmmc0>(0);
|
||||
write<Clk_src_mask_fsys::Mmc0_mask>(0);
|
||||
break;
|
||||
default:
|
||||
warning("Unsupported for ", names[id].name);
|
||||
}
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Constructor
|
||||
*/
|
||||
Cmu(Genode::Env &env)
|
||||
: Genode::Attached_mmio(env, CMU_MMIO_BASE, CMU_MMIO_SIZE),
|
||||
_cpu_freq(CPU_FREQ_1600)
|
||||
{
|
||||
/**
|
||||
* Close certain clock gates by default (~ 0.7 Watt reduction)
|
||||
*/
|
||||
write<Clk_gate_ip_acp>(0);
|
||||
write<Clk_gate_ip_isp0>(0);
|
||||
write<Clk_gate_ip_isp1>(0);
|
||||
write<Clk_gate_sclk_isp>(0);
|
||||
write<Clk_gate_ip_gscl>(0);
|
||||
write<Clk_gate_ip_disp1>(0);
|
||||
write<Clk_gate_ip_mfc>(0);
|
||||
write<Clk_gate_ip_g3d>(0);
|
||||
write<Clk_gate_ip_gen>(0);
|
||||
write<Clk_gate_ip_fsys>(0);
|
||||
write<Clk_gate_ip_peric>(Clk_gate_ip_peric::Clk_uart2::bits(1) |
|
||||
Clk_gate_ip_peric::Clk_pwm::bits(1));
|
||||
write<Clk_gate_block>(Clk_gate_block::Clk_gen::bits(1));
|
||||
|
||||
|
||||
/**
|
||||
* Set default CPU frequency
|
||||
*/
|
||||
_cpu_clk_freq(_cpu_freq);
|
||||
|
||||
/**
|
||||
* Hard wiring of certain reference clocks
|
||||
*/
|
||||
write<Pll_div2_sel::Mpll_fout_sel>(Pll_div2_sel::Mpll_fout_sel::MPLL_FOUT_HALF);
|
||||
write<Clk_src_core1::Mux_mpll_sel>(Clk_src_core1::Mux_mpll_sel::MPLL_FOUT_RGT);
|
||||
write<Clk_src_top2::Mux_mpll_user_sel>(Clk_src_top2::Mux_mpll_user_sel::MOUT_MPLL);
|
||||
write<Clk_src_fsys::Sata_sel>(Clk_src_fsys::Sata_sel::SCLK_MPLL_USER);
|
||||
write<Clk_src_fsys::Usbdrd30_sel>(Clk_src_fsys::Usbdrd30_sel::SCLK_MPLL_USER);
|
||||
}
|
||||
|
||||
|
||||
/********************************
|
||||
** Regulator driver interface **
|
||||
********************************/
|
||||
|
||||
void level(Regulator_id id, unsigned long level) override
|
||||
{
|
||||
switch (id) {
|
||||
case CLK_CPU:
|
||||
_cpu_clk_freq(level);
|
||||
break;
|
||||
default:
|
||||
warning("Unsupported for ", names[id].name);
|
||||
}
|
||||
}
|
||||
|
||||
unsigned long level(Regulator_id id) override
|
||||
{
|
||||
switch (id) {
|
||||
case CLK_CPU:
|
||||
return _cpu_freq;
|
||||
case CLK_USB30:
|
||||
case CLK_SATA:
|
||||
return 66666666; /* 66 MHz */
|
||||
default:
|
||||
warning("Unsupported for ", names[id].name);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void state(Regulator_id id, bool enable) override
|
||||
{
|
||||
if (enable)
|
||||
_enable(id);
|
||||
else
|
||||
_disable(id);
|
||||
}
|
||||
|
||||
bool state(Regulator_id id) override
|
||||
{
|
||||
switch (id) {
|
||||
case CLK_SATA:
|
||||
return read<Clk_gate_ip_fsys::Sata>() &&
|
||||
read<Clk_gate_ip_fsys::Sata_phy_ctrl>() &&
|
||||
read<Clk_src_mask_fsys::Sata_mask>();
|
||||
case CLK_USB30:
|
||||
return read<Clk_gate_ip_fsys::Usbdrd30>() &&
|
||||
read<Clk_src_mask_fsys::Usbdrd30_mask>();
|
||||
case CLK_USB20:
|
||||
return read<Clk_gate_ip_fsys::Usbhost20>();
|
||||
case CLK_MMC0:
|
||||
return read<Clk_gate_ip_fsys::Sdmmc0>() &&
|
||||
read<Clk_src_mask_fsys::Mmc0_mask>();
|
||||
default:
|
||||
warning("Unsupported for ", names[id].name);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
const Genode::uint8_t Cmu::s_values[] = { 2, 1, 1, 0, 0, 0, 0, 0, 0 };
|
||||
const Genode::uint16_t Cmu::m_values[] = { 100, 100, 200, 100, 125,
|
||||
150, 175, 200, 425 };
|
||||
const Genode::uint8_t Cmu::p_values[] = { 3, 3, 4, 3, 3, 3, 3, 3, 6 };
|
||||
const Genode::uint32_t Cmu::Clk_div_cpu0::values[] = { 0x1117710, 0x1127710, 0x1137710,
|
||||
0x2147710, 0x2147710, 0x3157720,
|
||||
0x4167720, 0x4177730, 0x5377730 };
|
||||
#endif /* _DRIVERS__PLATFORM__SPEC__ARNDALE__CMU_H_ */
|
||||
72
src/drivers/platform/spec/arndale/main.cc
Normal file
72
src/drivers/platform/spec/arndale/main.cc
Normal file
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* \brief Driver for Arndale specific platform devices (clocks, power, etc.)
|
||||
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
|
||||
* \date 2013-06-13
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <base/log.h>
|
||||
#include <base/heap.h>
|
||||
#include <base/component.h>
|
||||
#include <regulator/component.h>
|
||||
#include <regulator/consts.h>
|
||||
|
||||
#include <cmu.h>
|
||||
#include <pmu.h>
|
||||
|
||||
|
||||
struct Driver_factory : Regulator::Driver_factory
|
||||
{
|
||||
Cmu _cmu;
|
||||
Pmu _pmu;
|
||||
|
||||
Driver_factory(Genode::Env &env) : _cmu(env), _pmu(env) { }
|
||||
|
||||
Regulator::Driver &create(Regulator::Regulator_id id) override
|
||||
{
|
||||
switch (id) {
|
||||
case Regulator::CLK_CPU:
|
||||
case Regulator::CLK_SATA:
|
||||
case Regulator::CLK_USB30:
|
||||
case Regulator::CLK_USB20:
|
||||
case Regulator::CLK_MMC0:
|
||||
case Regulator::CLK_HDMI:
|
||||
return _cmu;
|
||||
case Regulator::PWR_SATA:
|
||||
case Regulator::PWR_USB30:
|
||||
case Regulator::PWR_USB20:
|
||||
case Regulator::PWR_HDMI:
|
||||
return _pmu;
|
||||
default:
|
||||
throw Genode::Service_denied(); /* invalid regulator */
|
||||
};
|
||||
}
|
||||
|
||||
void destroy(Regulator::Driver &) override { }
|
||||
};
|
||||
|
||||
|
||||
struct Main
|
||||
{
|
||||
Genode::Env & env;
|
||||
Genode::Heap heap { env.ram(), env.rm() };
|
||||
::Driver_factory factory { env };
|
||||
Regulator::Root root { env, heap, factory };
|
||||
|
||||
Main(Genode::Env & env) : env(env) {
|
||||
env.parent().announce(env.ep().manage(root)); }
|
||||
};
|
||||
|
||||
|
||||
void Component::construct(Genode::Env &env)
|
||||
{
|
||||
Genode::log("--- Arndale platform driver ---");
|
||||
|
||||
static Main main(env);
|
||||
}
|
||||
237
src/drivers/platform/spec/arndale/pmu.h
Normal file
237
src/drivers/platform/spec/arndale/pmu.h
Normal file
@@ -0,0 +1,237 @@
|
||||
/*
|
||||
* \brief Regulator driver for power management unit of Exynos5250 SoC
|
||||
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
|
||||
* \date 2013-06-18
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _DRIVERS__PLATFORM__SPEC__ARNDALE__PMU_H_
|
||||
#define _DRIVERS__PLATFORM__SPEC__ARNDALE__PMU_H_
|
||||
|
||||
#include <base/log.h>
|
||||
#include <regulator/consts.h>
|
||||
#include <regulator/driver.h>
|
||||
#include <os/attached_mmio.h>
|
||||
|
||||
using namespace Regulator;
|
||||
using Genode::warning;
|
||||
|
||||
class Pmu : public Regulator::Driver,
|
||||
private Genode::Attached_mmio
|
||||
{
|
||||
private:
|
||||
|
||||
enum {
|
||||
PMU_MMIO_BASE = 0x10040000,
|
||||
PMU_MMIO_SIZE = 0x5000,
|
||||
};
|
||||
|
||||
template <unsigned OFFSET>
|
||||
struct Control : Register <OFFSET, 32>
|
||||
{
|
||||
struct Enable : Register<OFFSET, 32>::template Bitfield<0, 1> { };
|
||||
};
|
||||
|
||||
template <unsigned OFFSET>
|
||||
struct Configuration : Register <OFFSET, 32>
|
||||
{
|
||||
struct Local_pwr_cfg : Register<OFFSET, 32>::template Bitfield<0, 3> { };
|
||||
};
|
||||
|
||||
template <unsigned OFFSET>
|
||||
struct Status : Register <OFFSET, 32>
|
||||
{
|
||||
struct Stat : Register<OFFSET, 32>::template Bitfield<0, 3> { };
|
||||
};
|
||||
|
||||
template <unsigned OFFSET>
|
||||
struct Sysclk_configuration : Register <OFFSET, 32>
|
||||
{
|
||||
struct Local_pwr_cfg : Register<OFFSET, 32>::template Bitfield<0, 1> { };
|
||||
};
|
||||
|
||||
template <unsigned OFFSET>
|
||||
struct Sysclk_status : Register <OFFSET, 32>
|
||||
{
|
||||
struct Stat : Register<OFFSET, 32>::template Bitfield<0, 1> { };
|
||||
};
|
||||
|
||||
struct Hdmi_phy_control : Register<0x700, 32>
|
||||
{
|
||||
struct Enable : Bitfield<0, 1> { };
|
||||
struct Div_ratio : Bitfield<16, 10> { };
|
||||
};
|
||||
|
||||
typedef Control<0x704> Usbdrd_phy_control;
|
||||
typedef Control<0x708> Usbhost_phy_control;
|
||||
typedef Control<0x70c> Efnand_phy_control;
|
||||
typedef Control<0x718> Adc_phy_control;
|
||||
typedef Control<0x71c> Mtcadc_phy_control;
|
||||
typedef Control<0x720> Dptx_phy_control;
|
||||
typedef Control<0x724> Sata_phy_control;
|
||||
|
||||
typedef Sysclk_configuration<0x2a40> Vpll_sysclk_configuration;
|
||||
typedef Sysclk_status<0x2a44> Vpll_sysclk_status;
|
||||
typedef Sysclk_configuration<0x2a60> Epll_sysclk_configuration;
|
||||
typedef Sysclk_status<0x2a64> Epll_sysclk_status;
|
||||
typedef Sysclk_configuration<0x2aa0> Cpll_sysclk_configuration;
|
||||
typedef Sysclk_status<0x2aa4> Cpll_sysclk_status;
|
||||
typedef Sysclk_configuration<0x2ac0> Gpll_sysclk_configuration;
|
||||
typedef Sysclk_status<0x2ac4> Gpll_sysclk_status;
|
||||
|
||||
typedef Configuration<0x4000> Gscl_configuration;
|
||||
typedef Status<0x4004> Gscl_status;
|
||||
typedef Configuration<0x4020> Isp_configuration;
|
||||
typedef Status<0x4024> Isp_status;
|
||||
typedef Configuration<0x4040> Mfc_configuration;
|
||||
typedef Status<0x4044> Mfc_status;
|
||||
typedef Configuration<0x4060> G3d_configuration;
|
||||
typedef Status<0x4064> G3d_status;
|
||||
typedef Configuration<0x40A0> Disp1_configuration;
|
||||
typedef Status<0x40A4> Disp1_status;
|
||||
typedef Configuration<0x40C0> Mau_configuration;
|
||||
typedef Status<0x40C4> Mau_status;
|
||||
|
||||
|
||||
template <typename C, typename S>
|
||||
void _disable_domain()
|
||||
{
|
||||
if (read<typename S::Stat>() == 0)
|
||||
return;
|
||||
write<typename C::Local_pwr_cfg>(0);
|
||||
while (read<typename S::Stat>() != 0) ;
|
||||
}
|
||||
|
||||
template <typename C, typename S>
|
||||
void _enable_domain()
|
||||
{
|
||||
if (read<typename S::Stat>() == 7)
|
||||
return;
|
||||
write<typename C::Local_pwr_cfg>(7);
|
||||
while (read<typename S::Stat>() != 7) ;
|
||||
}
|
||||
|
||||
void _enable(unsigned long id)
|
||||
{
|
||||
switch (id) {
|
||||
case PWR_USB30:
|
||||
write<Usbdrd_phy_control::Enable>(1);
|
||||
break;
|
||||
case PWR_USB20:
|
||||
write<Usbhost_phy_control::Enable>(1);
|
||||
break;
|
||||
case PWR_SATA :
|
||||
write<Sata_phy_control::Enable>(1);
|
||||
break;
|
||||
case PWR_HDMI: {
|
||||
_enable_domain<Disp1_configuration, Disp1_status>();
|
||||
Hdmi_phy_control::access_t hpc = read<Hdmi_phy_control>();
|
||||
Hdmi_phy_control::Div_ratio::set(hpc, 150);
|
||||
Hdmi_phy_control::Enable::set(hpc, 1);
|
||||
write<Hdmi_phy_control>(hpc);
|
||||
break; }
|
||||
default:
|
||||
warning("Unsupported for ", names[id].name);
|
||||
}
|
||||
}
|
||||
|
||||
void _disable(unsigned long id)
|
||||
{
|
||||
switch (id) {
|
||||
case PWR_USB30:
|
||||
write<Usbdrd_phy_control::Enable>(0);
|
||||
break;
|
||||
case PWR_USB20:
|
||||
write<Usbhost_phy_control::Enable>(0);
|
||||
break;
|
||||
case PWR_SATA :
|
||||
write<Sata_phy_control::Enable>(0);
|
||||
break;
|
||||
default:
|
||||
warning("Unsupported for ", names[id].name);
|
||||
}
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Constructor
|
||||
*/
|
||||
Pmu(Genode::Env &env)
|
||||
: Genode::Attached_mmio(env, PMU_MMIO_BASE, PMU_MMIO_SIZE)
|
||||
{
|
||||
write<Hdmi_phy_control ::Enable>(0);
|
||||
write<Usbdrd_phy_control ::Enable>(0);
|
||||
write<Usbhost_phy_control::Enable>(0);
|
||||
write<Efnand_phy_control ::Enable>(0);
|
||||
write<Adc_phy_control ::Enable>(0);
|
||||
write<Mtcadc_phy_control ::Enable>(0);
|
||||
write<Dptx_phy_control ::Enable>(0);
|
||||
write<Sata_phy_control ::Enable>(0);
|
||||
|
||||
_disable_domain<Gscl_configuration, Gscl_status>();
|
||||
_disable_domain<Isp_configuration, Isp_status>();
|
||||
_disable_domain<Mfc_configuration, Mfc_status>();
|
||||
_disable_domain<G3d_configuration, G3d_status>();
|
||||
_disable_domain<Disp1_configuration, Disp1_status>();
|
||||
_disable_domain<Mau_configuration, Mau_status>();
|
||||
|
||||
_disable_domain<Vpll_sysclk_configuration, Vpll_sysclk_status>();
|
||||
_disable_domain<Epll_sysclk_configuration, Epll_sysclk_status>();
|
||||
_disable_domain<Cpll_sysclk_configuration, Cpll_sysclk_status>();
|
||||
_disable_domain<Gpll_sysclk_configuration, Gpll_sysclk_status>();
|
||||
}
|
||||
|
||||
|
||||
/********************************
|
||||
** Regulator driver interface **
|
||||
********************************/
|
||||
|
||||
void level(Regulator_id id, unsigned long /* level */) override
|
||||
{
|
||||
switch (id) {
|
||||
default:
|
||||
warning("Unsupported for ", names[id].name);
|
||||
}
|
||||
}
|
||||
|
||||
unsigned long level(Regulator_id id) override
|
||||
{
|
||||
switch (id) {
|
||||
default:
|
||||
warning("Unsupported for ", names[id].name);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void state(Regulator_id id, bool enable) override
|
||||
{
|
||||
if (enable)
|
||||
_enable(id);
|
||||
else
|
||||
_disable(id);
|
||||
}
|
||||
|
||||
bool state(Regulator_id id) override
|
||||
{
|
||||
switch (id) {
|
||||
case PWR_USB30:
|
||||
return read<Usbdrd_phy_control::Enable>();
|
||||
case PWR_USB20:
|
||||
return read<Usbhost_phy_control::Enable>();
|
||||
case PWR_SATA:
|
||||
return read<Sata_phy_control::Enable>();
|
||||
default:
|
||||
warning("Unsupported for ", names[id].name);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _DRIVERS__PLATFORM__SPEC__ARNDALE__PMU_H_ */
|
||||
5
src/drivers/platform/spec/arndale/target.mk
Normal file
5
src/drivers/platform/spec/arndale/target.mk
Normal file
@@ -0,0 +1,5 @@
|
||||
TARGET = arndale_platform_drv
|
||||
REQUIRES = arm_v7
|
||||
SRC_CC = main.cc
|
||||
INC_DIR += ${PRG_DIR} ${REP_DIR}/include/spec/exynos5
|
||||
LIBS = base
|
||||
443
src/drivers/sd_card/spec/exynos5/driver.cc
Normal file
443
src/drivers/sd_card/spec/exynos5/driver.cc
Normal file
@@ -0,0 +1,443 @@
|
||||
/*
|
||||
* \brief Exynos5-specific implementation of the Block::Driver interface
|
||||
* \author Sebastian Sumpf
|
||||
* \author Martin Stein
|
||||
* \date 2013-03-22
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* local includes */
|
||||
#include <driver.h>
|
||||
|
||||
using namespace Genode;
|
||||
using namespace Sd_card;
|
||||
|
||||
|
||||
Driver::Driver(Env &env)
|
||||
:
|
||||
Driver_base(env.ram()),
|
||||
Attached_mmio(env, MSH_BASE, MSH_SIZE), _env(env)
|
||||
{
|
||||
_irq.sigh(_irq_handler);
|
||||
_irq.ack_irq();
|
||||
|
||||
log("SD/MMC card detected");
|
||||
log("capacity: ", _card_info.capacity_mb(), " MiB");
|
||||
}
|
||||
|
||||
|
||||
void Driver::read_dma(Block::sector_t block_number,
|
||||
size_t block_count,
|
||||
addr_t buf_phys,
|
||||
Block::Packet_descriptor &pkt)
|
||||
{
|
||||
if (_block_transfer.pending) {
|
||||
throw Request_congestion(); }
|
||||
|
||||
if (!_setup_idmac_descriptor_table(block_count, buf_phys))
|
||||
throw Io_error();
|
||||
|
||||
_block_transfer.packet = pkt;
|
||||
_block_transfer.pending = true;
|
||||
|
||||
if (!_issue_command(Read_multiple_block(block_number))) {
|
||||
error("Read_multiple_block failed");
|
||||
throw Io_error();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void Driver::write_dma(Block::sector_t block_number,
|
||||
size_t block_count,
|
||||
addr_t buf_phys,
|
||||
Block::Packet_descriptor &pkt)
|
||||
{
|
||||
if (_block_transfer.pending) {
|
||||
throw Request_congestion(); }
|
||||
|
||||
if (!_setup_idmac_descriptor_table(block_count, buf_phys))
|
||||
throw Io_error();
|
||||
|
||||
_block_transfer.packet = pkt;
|
||||
_block_transfer.pending = true;
|
||||
|
||||
if (!_issue_command(Write_multiple_block(block_number))) {
|
||||
error("Read_multiple_block failed");
|
||||
throw Io_error();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
bool Driver::_reset()
|
||||
{
|
||||
Mmio::write<Ctrl::Reset>(0x7);
|
||||
try { wait_for(Attempts(100), Microseconds(1000), _delayer,
|
||||
Ctrl::Reset::Equal(0)); }
|
||||
catch (Polling_timeout) {
|
||||
error("Could not reset host contoller");
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
void Driver::_reset_fifo()
|
||||
{
|
||||
Mmio::write<Ctrl::Reset>(0x2);
|
||||
try { wait_for(Attempts(100), Microseconds(1000), _delayer,
|
||||
Ctrl::Reset::Equal(0)); }
|
||||
catch (Polling_timeout) {
|
||||
error("Could not reset fifo"); }
|
||||
}
|
||||
|
||||
|
||||
void Driver::_disable_irq()
|
||||
{
|
||||
Mmio::write<Rintsts>(~0U);
|
||||
Mmio::write<Intmask>(0);
|
||||
}
|
||||
|
||||
|
||||
bool Driver::_update_clock_registers()
|
||||
{
|
||||
Cmd::access_t cmd = 0;
|
||||
Cmd::Wait_prvdata_complete::set(cmd, 1);
|
||||
Cmd::Update_clock_registers_only::set(cmd, 1);
|
||||
Cmd::Start_cmd::set(cmd, 1);
|
||||
Mmio::write<Cmd>(cmd);
|
||||
|
||||
try { wait_for(_delayer, Cmd::Start_cmd::Equal(0)); }
|
||||
catch (Polling_timeout) {
|
||||
error("Update clock registers failed");
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
bool Driver::_setup_bus(unsigned clock_div)
|
||||
{
|
||||
/* set host clock divider */
|
||||
Mmio::write<Clkdiv>(clock_div);
|
||||
|
||||
if (!_update_clock_registers())
|
||||
return false;
|
||||
|
||||
/* enable clock for card 1 */
|
||||
Mmio::write<Clkena>(0x1);
|
||||
|
||||
if (!_update_clock_registers())
|
||||
return false;
|
||||
|
||||
_delayer.usleep(10 * 1000);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
Card_info Driver::_init()
|
||||
{
|
||||
Mmio::write<Pwren>(1);
|
||||
if (!_reset())
|
||||
throw Detection_failed();
|
||||
|
||||
Mmio::write<Emmc_ddr_req>(0x1);
|
||||
|
||||
_disable_irq();
|
||||
|
||||
Mmio::write<Tmout>(~0U);
|
||||
Mmio::write<Idinten>(0);
|
||||
Mmio::write<Bmod>(1);
|
||||
Mmio::write<Bytcnt>(0);
|
||||
Mmio::write<Fifoth>(0x203f0040);
|
||||
|
||||
/* set to one bit transfer Bit */
|
||||
if (!_setup_bus(CLK_DIV_400Khz))
|
||||
throw Detection_failed();
|
||||
|
||||
Mmio::write<Ctype>(BUS_WIDTH_1);
|
||||
|
||||
if (!issue_command(Go_idle_state())) {
|
||||
warning("Go_idle_state command failed");
|
||||
throw Detection_failed();
|
||||
}
|
||||
_delayer.usleep(2000);
|
||||
|
||||
if (!issue_command(Send_if_cond())) {
|
||||
warning("Send_if_cond command failed");
|
||||
throw Detection_failed();
|
||||
}
|
||||
/* if this succeeds it is an SD card */
|
||||
if ((Mmio::read<Rsp0>() & 0xff) == 0xaa)
|
||||
log("Found SD card");
|
||||
|
||||
/*
|
||||
* We need to issue the same Mmc_send_op_cond command multiple
|
||||
* times. The first time, we receive the status information. On
|
||||
* subsequent attempts, the response tells us that the card is
|
||||
* busy. Usually, the command is issued twice. We give up if the
|
||||
* card is not reaching busy state after one second.
|
||||
*/
|
||||
unsigned i = 1000;
|
||||
unsigned voltages = 0x300080;
|
||||
unsigned arg = 0;
|
||||
for (; i > 0; --i) {
|
||||
if (!issue_command(Mmc_send_op_cond(arg, true))) {
|
||||
warning("Sd_send_op_cond command failed");
|
||||
throw Detection_failed();
|
||||
}
|
||||
arg = Mmio::read<Rsp0>();
|
||||
arg = (voltages & (arg & 0x007FFF80)) | (arg & 0x60000000);
|
||||
|
||||
_delayer.usleep(1000);
|
||||
|
||||
if (Ocr::Busy::get(Mmio::read<Rsp0>()))
|
||||
break;
|
||||
}
|
||||
if (i == 0) {
|
||||
error("Send_op_cond timed out, could no power-on SD/MMC card");
|
||||
throw Detection_failed();
|
||||
}
|
||||
Card_info card_info = _detect_mmc();
|
||||
|
||||
/* switch frequency to high speed */
|
||||
enum { EXT_CSD_HS_TIMING = 185 };
|
||||
if (!issue_command(Mmc_switch(EXT_CSD_HS_TIMING, 1))) {
|
||||
error("Error setting high speed frequency");
|
||||
throw Detection_failed();
|
||||
}
|
||||
enum { EXT_CSD_BUS_WIDTH = 183 };
|
||||
/* set card to 8 bit */
|
||||
if (!issue_command(Mmc_switch(EXT_CSD_BUS_WIDTH, 2))) {
|
||||
error("Error setting card bus width");
|
||||
throw Detection_failed();
|
||||
}
|
||||
Mmio::write<Ctype>(BUS_WIDTH_8);
|
||||
|
||||
/* set to eight bit transfer Bit */
|
||||
if (!_setup_bus(CLK_DIV_52Mhz)) {
|
||||
error("Error setting bus to high speed");
|
||||
throw Detection_failed();
|
||||
}
|
||||
/* Enable IRQs data read timeout, data transfer done, resp error */
|
||||
Mmio::write<Intmask>(0x28a);
|
||||
Mmio::write<Ctrl::Global_interrupt>(1);
|
||||
return card_info;
|
||||
}
|
||||
|
||||
|
||||
bool Driver::_setup_idmac_descriptor_table(size_t block_count,
|
||||
addr_t phys_addr)
|
||||
{
|
||||
size_t const max_idmac_block_count = IDMAC_DESC_MAX_ENTRIES * 8;
|
||||
|
||||
if (block_count > max_idmac_block_count) {
|
||||
error("Block request too large");
|
||||
return false;
|
||||
}
|
||||
_reset_fifo();
|
||||
|
||||
Idmac_desc::Flags flags = Idmac_desc::FS;
|
||||
size_t b = block_count;
|
||||
int index = 0;
|
||||
for (index = 0; b; index++, phys_addr += 0x1000, flags = Idmac_desc::NONE) {
|
||||
b = _idmac_desc[index].set(b, _block_size(), phys_addr, flags);
|
||||
_idmac_desc[index].next =
|
||||
_idmac_desc_phys + ((index + 1) * sizeof(Idmac_desc));
|
||||
}
|
||||
_idmac_desc[index].next = (unsigned)_idmac_desc;
|
||||
_idmac_desc[index].flags |= Idmac_desc::ER;
|
||||
Mmio::write<Dbaddr>(_idmac_desc_phys);
|
||||
|
||||
Mmio::write<Ctrl::Dma_enable>(1);
|
||||
Mmio::write<Ctrl::Use_internal_dmac>(1);
|
||||
|
||||
Mmio::write<Bmod::Fixed_burst>(1);
|
||||
Mmio::write<Bmod::Idmac_enable>(1);
|
||||
|
||||
Mmio::write<Blksize>(_block_size());
|
||||
Mmio::write<Bytcnt>(_block_size() * block_count);
|
||||
|
||||
Mmio::write<Pldmnd>(1);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
void Driver::_handle_irq()
|
||||
{
|
||||
_irq.ack_irq();
|
||||
|
||||
if (!_block_transfer.pending) {
|
||||
return; }
|
||||
|
||||
bool success = false;
|
||||
if (Mmio::read<Rintsts::Response_error>()) {
|
||||
error("Response error");
|
||||
}
|
||||
if (Mmio::read<Rintsts::Data_read_timeout>()) {
|
||||
error("Data read timeout");
|
||||
}
|
||||
if (Mmio::read<Rintsts::Data_crc_error>()) {
|
||||
error("CRC error");
|
||||
}
|
||||
if (Mmio::read<Rintsts::Data_transfer_over>()) {
|
||||
Mmio::write<Rintsts>(~0U);
|
||||
if (!_issue_command(Stop_transmission())) {
|
||||
error("unable to stop transmission");
|
||||
} else {
|
||||
success = true;
|
||||
}
|
||||
}
|
||||
_block_transfer.pending = false;
|
||||
ack_packet(_block_transfer.packet, success);
|
||||
}
|
||||
|
||||
|
||||
bool Driver::_issue_command(Command_base const &command)
|
||||
{
|
||||
try { wait_for(Attempts(10000), Microseconds(100), _delayer,
|
||||
Status::Data_busy::Equal(0)); }
|
||||
catch (Polling_timeout) {
|
||||
error("wait for State::Data_busy timed out ",
|
||||
Hex(Mmio::read<Status>()));
|
||||
return false;
|
||||
}
|
||||
|
||||
Mmio::write<Rintsts>(~0UL);
|
||||
|
||||
/* write command argument */
|
||||
Mmio::write<Cmdarg>(command.arg);
|
||||
|
||||
Cmd::access_t cmd = 0;
|
||||
Cmd::Index::set(cmd, command.index);
|
||||
|
||||
if (command.transfer != TRANSFER_NONE) {
|
||||
/* set data-direction bit depending on the command */
|
||||
bool const write = command.transfer == TRANSFER_WRITE;
|
||||
Cmd::Data_expected::set(cmd, 1);
|
||||
Cmd::Write::set(cmd, write ? 1 : 0);
|
||||
}
|
||||
|
||||
Cmd::access_t rsp_type = 0;
|
||||
switch (command.rsp_type) {
|
||||
case RESPONSE_NONE: rsp_type = Cmd::Rsp_type::RESPONSE_NONE; break;
|
||||
case RESPONSE_136_BIT: rsp_type = Cmd::Rsp_type::RESPONSE_136_BIT; break;
|
||||
case RESPONSE_48_BIT: rsp_type = Cmd::Rsp_type::RESPONSE_48_BIT; break;
|
||||
case RESPONSE_48_BIT_WITH_BUSY: rsp_type = Cmd::Rsp_type::RESPONSE_48_BIT_WITH_BUSY; break;
|
||||
}
|
||||
|
||||
Cmd::Rsp_type::set(cmd, rsp_type);
|
||||
Cmd::Start_cmd::set(cmd, 1);
|
||||
Cmd::Use_hold_reg::set(cmd ,1);
|
||||
Cmd::Wait_prvdata_complete::set(cmd, 1);
|
||||
|
||||
if (command.index == 0)
|
||||
Cmd::Init_sequence::set(cmd, 1);
|
||||
|
||||
/* issue command */
|
||||
Mmio::write<Cmd>(cmd);
|
||||
|
||||
try { wait_for(Attempts(10000), Microseconds(100), _delayer,
|
||||
Rintsts::Command_done::Equal(1)); }
|
||||
catch (Polling_timeout) {
|
||||
error("command failed "
|
||||
"Rintst: ", Mmio::read<Rintsts>(), " "
|
||||
"Mintst: ", Mmio::read<Mintsts>(), " "
|
||||
"Status: ", Mmio::read<Status>());
|
||||
|
||||
if (Mmio::read<Rintsts::Response_timeout>())
|
||||
warning("timeout");
|
||||
|
||||
if (Mmio::read<Rintsts::Response_error>())
|
||||
warning("repsonse error");
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/* acknowledge interrupt */
|
||||
Mmio::write<Rintsts::Command_done>(1);
|
||||
|
||||
_delayer.usleep(100);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
Cid Driver::_read_cid()
|
||||
{
|
||||
Cid cid;
|
||||
cid.raw_0 = Mmio::read<Rsp0>();
|
||||
cid.raw_1 = Mmio::read<Rsp1>();
|
||||
cid.raw_2 = Mmio::read<Rsp2>();
|
||||
cid.raw_3 = Mmio::read<Rsp3>();
|
||||
return cid;
|
||||
}
|
||||
|
||||
|
||||
Csd Driver::_read_csd()
|
||||
{
|
||||
Csd csd;
|
||||
csd.csd0 = Mmio::read<Rsp0>();
|
||||
csd.csd1 = Mmio::read<Rsp1>();
|
||||
csd.csd2 = Mmio::read<Rsp2>();
|
||||
csd.csd3 = Mmio::read<Rsp3>();
|
||||
return csd;
|
||||
}
|
||||
|
||||
|
||||
size_t Driver::_read_ext_csd()
|
||||
{
|
||||
Attached_ram_dataspace ds(_env.ram(), _env.rm(), 0x1000, UNCACHED);
|
||||
|
||||
addr_t phys = Dataspace_client(ds.cap()).phys_addr();
|
||||
_setup_idmac_descriptor_table(1, phys);
|
||||
|
||||
if (!issue_command(Mmc_send_ext_csd()))
|
||||
throw Detection_failed();
|
||||
|
||||
try { wait_for(_delayer, Rintsts::Data_transfer_over::Equal(1)); }
|
||||
catch (Polling_timeout) {
|
||||
error("cannot retrieve extented CSD");
|
||||
throw Detection_failed();
|
||||
}
|
||||
/* clear IRQ */
|
||||
Mmio::write<Rintsts::Data_transfer_over>(1);
|
||||
|
||||
/* contruct extented CSD */
|
||||
Ext_csd csd((addr_t)ds.local_addr<addr_t>());
|
||||
|
||||
/* read revision */
|
||||
if (csd.Mmio::read<Ext_csd::Revision>() < 2) {
|
||||
error("extented CSD revision is < 2");
|
||||
throw Detection_failed();
|
||||
}
|
||||
|
||||
/* return sector count */
|
||||
uint64_t capacity = csd.Mmio::read<Ext_csd::Sector_count>() * _block_size();
|
||||
|
||||
/* to MB */
|
||||
return capacity / (1024 * 1024);
|
||||
}
|
||||
|
||||
|
||||
size_t Driver::Idmac_desc::set(size_t block_count,
|
||||
size_t block_size,
|
||||
addr_t phys_addr,
|
||||
Flags flag)
|
||||
{
|
||||
constexpr size_t MAX_BLOCKS = 8;
|
||||
flags = OWN | flag |
|
||||
(block_count <= MAX_BLOCKS ? LD : (CH | DIC));
|
||||
bytes = ((block_count < MAX_BLOCKS) ? block_count : MAX_BLOCKS) *
|
||||
block_size;
|
||||
addr = phys_addr;
|
||||
|
||||
return block_count < MAX_BLOCKS ?
|
||||
0 : block_count - MAX_BLOCKS;
|
||||
}
|
||||
246
src/drivers/sd_card/spec/exynos5/driver.h
Normal file
246
src/drivers/sd_card/spec/exynos5/driver.h
Normal file
@@ -0,0 +1,246 @@
|
||||
/*
|
||||
* \brief Exynos5-specific implementation of the Block::Driver interface
|
||||
* \author Sebastian Sumpf
|
||||
* \author Martin Stein
|
||||
* \date 2013-03-22
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _DRIVER_H_
|
||||
#define _DRIVER_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <os/attached_mmio.h>
|
||||
#include <timer_session/connection.h>
|
||||
#include <regulator_session/connection.h>
|
||||
#include <irq_session/connection.h>
|
||||
#include <base/attached_ram_dataspace.h>
|
||||
|
||||
/* local includes */
|
||||
#include <driver_base.h>
|
||||
|
||||
namespace Sd_card { class Driver; }
|
||||
|
||||
|
||||
class Sd_card::Driver : public Driver_base,
|
||||
private Attached_mmio
|
||||
{
|
||||
private:
|
||||
|
||||
/*
|
||||
* Noncopyable
|
||||
*/
|
||||
Driver(Driver const &);
|
||||
Driver &operator = (Driver const &);
|
||||
|
||||
enum {
|
||||
HOST_FREQ = 52000000,
|
||||
CLK_FREQ = 400000000,
|
||||
CLK_DIV_52Mhz = 4,
|
||||
CLK_DIV_400Khz = 0xff,
|
||||
MSH_BASE = 0x12200000,
|
||||
MSH_SIZE = 0x10000,
|
||||
IDMAC_DESC_MAX_ENTRIES = 1024,
|
||||
SDMMC0_IRQ = 107,
|
||||
};
|
||||
|
||||
enum Bus_width {
|
||||
BUS_WIDTH_1 = 0,
|
||||
BUS_WIDTH_4 = 1,
|
||||
BUS_WIDTH_8 = 1 << 16,
|
||||
};
|
||||
|
||||
template <off_t OFFSET, bool STRICT_WRITE = false>
|
||||
struct Register : Mmio::Register<OFFSET, 32, STRICT_WRITE> { };
|
||||
|
||||
struct Ctrl : Register<0x0>
|
||||
{
|
||||
struct Reset : Bitfield<0, 3> { };
|
||||
struct Global_interrupt : Bitfield<4, 1> { };
|
||||
struct Dma_enable : Bitfield<5, 1> { };
|
||||
struct Use_internal_dmac : Bitfield<25, 1> { };
|
||||
};
|
||||
|
||||
struct Pwren : Register<0x4> { };
|
||||
struct Clkdiv : Register<0x8> { };
|
||||
struct Clkena : Register<0x10> { };
|
||||
struct Tmout : Register<0x14> { };
|
||||
struct Ctype : Register<0x18, true> { };
|
||||
struct Blksize : Register<0x1c> { };
|
||||
struct Bytcnt : Register<0x20> { };
|
||||
struct Intmask : Register<0x24> { };
|
||||
struct Cmdarg : Register<0x28> { };
|
||||
|
||||
struct Cmd : Register<0x2c>
|
||||
{
|
||||
struct Index : Bitfield<0, 6> { };
|
||||
struct Rsp_type : Bitfield<6, 3>
|
||||
{
|
||||
enum Response { RESPONSE_NONE = 0,
|
||||
RESPONSE_48_BIT = 1,
|
||||
RESPONSE_48_BIT_WITH_BUSY = 5,
|
||||
RESPONSE_136_BIT = 7,
|
||||
};
|
||||
};
|
||||
struct Data_expected : Bitfield<9, 1> { };
|
||||
struct Write : Bitfield<10, 1> { };
|
||||
struct Wait_prvdata_complete : Bitfield<13, 1> { };
|
||||
struct Init_sequence : Bitfield<15, 1> { };
|
||||
struct Update_clock_registers_only : Bitfield<21, 1> { };
|
||||
struct Use_hold_reg : Bitfield<29, 1> { };
|
||||
struct Start_cmd : Bitfield<31, 1> { };
|
||||
};
|
||||
|
||||
struct Rsp0 : Register<0x30> { };
|
||||
struct Rsp1 : Register<0x34> { };
|
||||
struct Rsp2 : Register<0x38> { };
|
||||
struct Rsp3 : Register<0x3c> { };
|
||||
|
||||
struct Mintsts : Register<0x40> { };
|
||||
struct Rintsts : Register<0x44, true>
|
||||
{
|
||||
struct Response_error : Bitfield<1, 1> { };
|
||||
struct Data_transfer_over : Bitfield<3, 1> { };
|
||||
struct Command_done : Bitfield<2, 1> { };
|
||||
struct Data_crc_error : Bitfield<7, 1> { };
|
||||
struct Response_timeout : Bitfield<8, 1> { };
|
||||
struct Data_read_timeout : Bitfield<9, 1> { };
|
||||
};
|
||||
|
||||
struct Status : Register<0x48>
|
||||
{
|
||||
struct Data_busy : Bitfield<9, 1> { };
|
||||
};
|
||||
|
||||
struct Fifoth : Register<0x4c> { };
|
||||
|
||||
struct Bmod : Register<0x80, true>
|
||||
{
|
||||
struct Fixed_burst : Bitfield<1, 1> { };
|
||||
struct Idmac_enable : Bitfield<7, 1> { };
|
||||
};
|
||||
|
||||
struct Pldmnd : Register<0x84> { };
|
||||
struct Idsts : Register<0x8c> { };
|
||||
struct Idinten : Register<0x90, true> { };
|
||||
struct Dbaddr : Register<0x88> { };
|
||||
struct Clksel : Register<0x9c> { };
|
||||
struct Emmc_ddr_req : Register<0x10c, true> { };
|
||||
|
||||
struct Idmac_desc
|
||||
{
|
||||
enum Flags {
|
||||
NONE = 0,
|
||||
DIC = 1 << 1,
|
||||
LD = 1 << 2,
|
||||
FS = 1 << 3,
|
||||
CH = 1 << 4,
|
||||
ER = 1 << 5,
|
||||
OWN = 1 << 31,
|
||||
};
|
||||
|
||||
unsigned flags;
|
||||
unsigned bytes;
|
||||
unsigned addr;
|
||||
unsigned next;
|
||||
|
||||
size_t set(size_t block_count,
|
||||
size_t block_size,
|
||||
addr_t phys_addr,
|
||||
Flags flag);
|
||||
};
|
||||
|
||||
struct Clock_regulator
|
||||
{
|
||||
Regulator::Connection regulator;
|
||||
|
||||
Clock_regulator(Env &env) : regulator(env, Regulator::CLK_MMC0) {
|
||||
regulator.state(true); }
|
||||
};
|
||||
|
||||
struct Timer_delayer : Timer::Connection, Mmio::Delayer
|
||||
{
|
||||
Timer_delayer(Genode::Env &env) : Timer::Connection(env) { }
|
||||
|
||||
void usleep(uint64_t us) override { Timer::Connection::usleep(us); }
|
||||
};
|
||||
|
||||
struct Block_transfer
|
||||
{
|
||||
Block::Packet_descriptor packet { };
|
||||
bool pending = false;
|
||||
};
|
||||
|
||||
Env &_env;
|
||||
Timer_delayer _delayer { _env };
|
||||
Block_transfer _block_transfer { };
|
||||
Clock_regulator _clock_regulator { _env };
|
||||
Signal_handler<Driver> _irq_handler { _env.ep(), *this, &Driver::_handle_irq };
|
||||
Irq_connection _irq { _env, SDMMC0_IRQ };
|
||||
Attached_ram_dataspace _idmac_desc_ds { _env.ram(), _env.rm(),
|
||||
IDMAC_DESC_MAX_ENTRIES * sizeof(Idmac_desc),
|
||||
UNCACHED };
|
||||
Idmac_desc *const _idmac_desc { _idmac_desc_ds.local_addr<Idmac_desc>() };
|
||||
addr_t const _idmac_desc_phys { Dataspace_client(_idmac_desc_ds.cap())
|
||||
.phys_addr() };
|
||||
Card_info _card_info { _init() };
|
||||
|
||||
bool _reset();
|
||||
void _reset_fifo();
|
||||
void _disable_irq();
|
||||
bool _update_clock_registers();
|
||||
bool _setup_bus(unsigned clock_div);
|
||||
void _handle_irq();
|
||||
Card_info _init();
|
||||
|
||||
bool _setup_idmac_descriptor_table(size_t block_count,
|
||||
addr_t phys_addr);
|
||||
|
||||
|
||||
/*********************
|
||||
** Host_controller **
|
||||
*********************/
|
||||
|
||||
bool _issue_command(Command_base const &command) override;
|
||||
Cid _read_cid() override ;
|
||||
Csd _read_csd() override ;
|
||||
size_t _read_ext_csd() override;
|
||||
unsigned _read_rca() override { return 0; }
|
||||
|
||||
Card_info card_info() const override { return _card_info; }
|
||||
|
||||
public:
|
||||
|
||||
using Block::Driver::read;
|
||||
using Block::Driver::write;
|
||||
|
||||
Driver(Env &env);
|
||||
|
||||
|
||||
/*******************
|
||||
** Block::Driver **
|
||||
*******************/
|
||||
|
||||
void read_dma(Block::sector_t block_number,
|
||||
size_t block_count,
|
||||
addr_t buf_phys,
|
||||
Block::Packet_descriptor &pkt) override;
|
||||
|
||||
void write_dma(Block::sector_t block_number,
|
||||
size_t block_count,
|
||||
addr_t buf_phys,
|
||||
Block::Packet_descriptor &pkt) override;
|
||||
|
||||
bool dma_enabled() override { return true; }
|
||||
|
||||
Ram_dataspace_capability alloc_dma_buffer(size_t size) override {
|
||||
return _env.ram().alloc(size, UNCACHED); }
|
||||
};
|
||||
|
||||
#endif /* _DRIVER_H_ */
|
||||
10
src/drivers/sd_card/spec/exynos5/target.mk
Normal file
10
src/drivers/sd_card/spec/exynos5/target.mk
Normal file
@@ -0,0 +1,10 @@
|
||||
TARGET = exynos5_sd_card_drv
|
||||
REQUIRES = arm_v7
|
||||
SRC_CC += main.cc driver.cc
|
||||
LIBS += base
|
||||
INC_DIR += $(PRG_DIR)
|
||||
INC_DIR += $(BASE_DIR)/../os/src/drivers/sd_card
|
||||
INC_DIR += $(REP_DIR)/include/spec/exynos5
|
||||
|
||||
vpath %.cc $(BASE_DIR)/../os/src/drivers/sd_card
|
||||
vpath %.cc $(PRG_DIR)
|
||||
339
src/drivers/usb_host/spec/arndale/platform.cc
Normal file
339
src/drivers/usb_host/spec/arndale/platform.cc
Normal file
@@ -0,0 +1,339 @@
|
||||
/*
|
||||
* \brief EHCI for Arndale initialization code
|
||||
* \author Sebastian Sumpf
|
||||
* \date 2013-02-20
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is distributed under the terms of the GNU General Public License
|
||||
* version 2.
|
||||
*/
|
||||
|
||||
/* Genode */
|
||||
#include <base/attached_io_mem_dataspace.h>
|
||||
#include <io_mem_session/connection.h>
|
||||
#include <regulator/consts.h>
|
||||
#include <regulator_session/connection.h>
|
||||
#include <timer_session/connection.h>
|
||||
#include <util/mmio.h>
|
||||
|
||||
/* Emulation */
|
||||
#include <lx_emul.h>
|
||||
#include <platform.h>
|
||||
|
||||
|
||||
using namespace Genode;
|
||||
|
||||
enum {
|
||||
EHCI_BASE = 0x12110000,
|
||||
DWC3_BASE = 0x12000000,
|
||||
DWC3_PHY_BASE = 0x12100000,
|
||||
GPIO_BASE = 0x11400000,
|
||||
EHCI_IRQ = 103,
|
||||
DWC3_IRQ = 104,
|
||||
};
|
||||
|
||||
static resource _ehci[] =
|
||||
{
|
||||
{ EHCI_BASE, EHCI_BASE + 0xfff, "ehci", IORESOURCE_MEM },
|
||||
{ EHCI_IRQ, EHCI_IRQ, "ehci-irq", IORESOURCE_IRQ },
|
||||
};
|
||||
|
||||
static resource _dwc3[] =
|
||||
{
|
||||
{ DWC3_BASE, DWC3_BASE + 0xcfff, "dwc3", IORESOURCE_MEM },
|
||||
{ DWC3_IRQ, DWC3_IRQ, "dwc3-irq", IORESOURCE_IRQ },
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* EHCI controller
|
||||
*/
|
||||
struct Ehci : Genode::Mmio
|
||||
{
|
||||
Ehci(addr_t const mmio_base) : Mmio(mmio_base)
|
||||
{
|
||||
write<Cmd>(0);
|
||||
|
||||
/* reset */
|
||||
write<Cmd::Reset>(1);
|
||||
|
||||
while(read<Cmd::Reset>())
|
||||
msleep(1);
|
||||
}
|
||||
|
||||
struct Cmd : Register<0x10, 32>
|
||||
{
|
||||
struct Reset : Bitfield<1, 1> { };
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* Gpio handling
|
||||
*/
|
||||
struct Gpio_bank {
|
||||
unsigned con;
|
||||
unsigned dat;
|
||||
};
|
||||
|
||||
|
||||
static inline
|
||||
unsigned con_mask(unsigned val) { return 0xf << ((val) << 2); }
|
||||
|
||||
|
||||
static inline
|
||||
unsigned con_sfr(unsigned x, unsigned v) { return (v) << ((x) << 2); }
|
||||
|
||||
|
||||
static void gpio_cfg_pin(Gpio_bank *bank, int gpio, int cfg)
|
||||
{
|
||||
unsigned int value;
|
||||
|
||||
value = readl(&bank->con);
|
||||
value &= ~con_mask(gpio);
|
||||
value |= con_sfr(gpio, cfg);
|
||||
writel(value, &bank->con);
|
||||
}
|
||||
|
||||
|
||||
static void gpio_direction_output(Gpio_bank *bank, int gpio, int en)
|
||||
{
|
||||
unsigned int value;
|
||||
enum { GPIO_OUTPUT = 0x1 };
|
||||
|
||||
gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
|
||||
|
||||
value = readl(&bank->dat);
|
||||
value &= ~(0x1 << gpio);
|
||||
if (en)
|
||||
value |= 0x1 << gpio;
|
||||
writel(value, &bank->dat);
|
||||
}
|
||||
|
||||
|
||||
static void arndale_ehci_init(Genode::Env &env)
|
||||
{
|
||||
enum Gpio_offset { D1 = 0x180, X3 = 0xc60 };
|
||||
|
||||
/* enable USB3 clock and power up */
|
||||
static Regulator::Connection reg_clk(env, Regulator::CLK_USB20);
|
||||
reg_clk.state(true);
|
||||
|
||||
static Regulator::Connection reg_pwr(env, Regulator::PWR_USB20);
|
||||
reg_pwr.state(true);
|
||||
|
||||
/* reset hub via GPIO */
|
||||
Io_mem_connection io_gpio(env, GPIO_BASE, 0x1000);
|
||||
addr_t gpio_base = (addr_t)env.rm().attach(io_gpio.dataspace());
|
||||
|
||||
Gpio_bank *d1 = reinterpret_cast<Gpio_bank *>(gpio_base + D1);
|
||||
Gpio_bank *x3 = reinterpret_cast<Gpio_bank *>(gpio_base + X3);
|
||||
|
||||
/* hub reset */
|
||||
gpio_direction_output(x3, 5, 0);
|
||||
/* hub connect */
|
||||
gpio_direction_output(d1, 7, 0);
|
||||
|
||||
gpio_direction_output(x3, 5, 1);
|
||||
gpio_direction_output(d1, 7, 1);
|
||||
|
||||
env.rm().detach(gpio_base);
|
||||
|
||||
/* reset ehci controller */
|
||||
Io_mem_connection io_ehci(env, EHCI_BASE, 0x1000);
|
||||
addr_t ehci_base = (addr_t)env.rm().attach(io_ehci.dataspace());
|
||||
|
||||
Ehci ehci(ehci_base);
|
||||
env.rm().detach(ehci_base);
|
||||
}
|
||||
|
||||
|
||||
struct Phy_usb3 : Genode::Mmio
|
||||
{
|
||||
struct Link_system : Register<0x4, 32>
|
||||
{
|
||||
struct Fladj : Bitfield<1, 6> { };
|
||||
struct Ehci_version_control : Bitfield<27, 1> { };
|
||||
};
|
||||
|
||||
struct Phy_utmi : Register<0x8, 32> { };
|
||||
|
||||
struct Phy_clk_rst : Register<0x10, 32>
|
||||
{
|
||||
struct Common_onn : Bitfield<0, 1> { };
|
||||
struct Port_reset : Bitfield<1, 1> { };
|
||||
struct Ref_clk_sel : Bitfield<2, 2> { };
|
||||
struct Retenablen : Bitfield<4, 1> { };
|
||||
struct Fsel : Bitfield<5, 6> { };
|
||||
struct Mpll_mult : Bitfield<11, 7> { };
|
||||
struct Ref_ssp_en : Bitfield<19, 1> { };
|
||||
struct Ssc_en : Bitfield<20, 1> { };
|
||||
struct Ssc_ref_clk_sel : Bitfield<23, 8> { };
|
||||
};
|
||||
|
||||
struct Phy_reg0 : Register<0x14, 32> { };
|
||||
|
||||
struct Phy_param0 : Register<0x1c, 32>
|
||||
{
|
||||
struct Loss_level : Bitfield<26, 5> { };
|
||||
struct Ref_use_pad : Bitfield<31, 1> { };
|
||||
};
|
||||
|
||||
struct Phy_param1 : Register<0x20, 32>
|
||||
{
|
||||
struct Pcs_txdeemph : Bitfield<0, 5> { };
|
||||
};
|
||||
|
||||
struct Phy_test : Register<0x28, 32>
|
||||
{
|
||||
struct Power_down_ssb_hsb : Bitfield<2, 2> { };
|
||||
};
|
||||
|
||||
struct Phy_batchg : Register<0x30, 32>
|
||||
{
|
||||
struct Utmi_clksel : Bitfield<2, 1> { };
|
||||
};
|
||||
|
||||
struct Phy_resume : Register<0x34, 32> { };
|
||||
|
||||
Phy_usb3 (Genode::Env & env, addr_t const base) : Mmio(base)
|
||||
{
|
||||
Timer::Connection timer(env);
|
||||
|
||||
/* reset */
|
||||
write<Phy_reg0>(0);
|
||||
|
||||
/* clock source */
|
||||
write<Phy_param0::Ref_use_pad>(0);
|
||||
|
||||
/* set Loss-of-Signal Detector sensitivity */
|
||||
write<Phy_param0::Loss_level>(0x9);
|
||||
write<Phy_resume>(0);
|
||||
|
||||
/*
|
||||
* Setting the Frame length Adj value[6:1] to default 0x20
|
||||
* See xHCI 1.0 spec, 5.2.4
|
||||
*/
|
||||
write<Link_system::Ehci_version_control>(1);
|
||||
write<Link_system::Fladj>(0x20);
|
||||
|
||||
/* set Tx De-Emphasis level */
|
||||
write<Phy_param1::Pcs_txdeemph>(0x1c);
|
||||
|
||||
/* set clock */
|
||||
write<Phy_batchg::Utmi_clksel>(1);
|
||||
|
||||
/* PHYTEST POWERDOWN Control */
|
||||
write<Phy_test::Power_down_ssb_hsb>(0);
|
||||
|
||||
/* UTMI power */
|
||||
enum { OTG_DISABLE = (1 << 6) };
|
||||
write<Phy_utmi>(OTG_DISABLE);
|
||||
|
||||
/* setup clock */
|
||||
Phy_clk_rst::access_t clk = 0;
|
||||
|
||||
/*
|
||||
* Use same reference clock for high speed
|
||||
* as for super speed
|
||||
*/
|
||||
Phy_clk_rst::Ref_clk_sel::set(clk, 0x2);
|
||||
/* 24 MHz */
|
||||
Phy_clk_rst::Fsel::set(clk, 0x2a);
|
||||
Phy_clk_rst::Mpll_mult::set(clk, 0x68);
|
||||
Phy_clk_rst::Ssc_ref_clk_sel::set(clk, 0x88);
|
||||
|
||||
/* port reset */
|
||||
Phy_clk_rst::Port_reset::set(clk, 1);
|
||||
|
||||
/* digital power supply in normal operating mode */
|
||||
Phy_clk_rst::Retenablen::set(clk, 1);
|
||||
/* enable ref clock for SS function */
|
||||
Phy_clk_rst::Ref_ssp_en::set(clk, 1);
|
||||
/* enable spread spectrum */
|
||||
Phy_clk_rst::Ssc_en::set(clk, 1);
|
||||
/* power down HS Bias and PLL blocks in suspend mode */
|
||||
Phy_clk_rst::Common_onn::set(clk, 1);
|
||||
|
||||
write<Phy_clk_rst>(clk);
|
||||
timer.usleep(10);
|
||||
write<Phy_clk_rst::Port_reset>(0);
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
static void arndale_xhci_init(Genode::Env &env)
|
||||
{
|
||||
/* enable USB3 clock and power up */
|
||||
static Regulator::Connection reg_clk(env, Regulator::CLK_USB30);
|
||||
reg_clk.state(true);
|
||||
|
||||
static Regulator::Connection reg_pwr(env, Regulator::PWR_USB30);
|
||||
reg_pwr.state(true);
|
||||
|
||||
/* setup PHY */
|
||||
Attached_io_mem_dataspace io_phy(env, DWC3_PHY_BASE, 0x1000);
|
||||
Phy_usb3 phy(env, (addr_t)io_phy.local_addr<addr_t>());
|
||||
}
|
||||
|
||||
|
||||
extern "C" void module_ehci_exynos_init();
|
||||
extern "C" void module_dwc3_driver_init();
|
||||
extern "C" void module_xhci_plat_init();
|
||||
|
||||
|
||||
void ehci_setup(Services *services)
|
||||
{
|
||||
/* register EHCI controller */
|
||||
module_ehci_exynos_init();
|
||||
|
||||
/* setup controller */
|
||||
arndale_ehci_init(services->env);
|
||||
|
||||
/* setup EHCI-controller platform device */
|
||||
platform_device *pdev = (platform_device *)kzalloc(sizeof(platform_device), 0);
|
||||
pdev->name = (char *)"exynos-ehci";
|
||||
pdev->id = 0;
|
||||
pdev->num_resources = 2;
|
||||
pdev->resource = _ehci;
|
||||
|
||||
/*needed for DMA buffer allocation. See 'hcd_buffer_alloc' in 'buffer.c' */
|
||||
static u64 dma_mask = ~(u64)0;
|
||||
pdev->dev.dma_mask = &dma_mask;
|
||||
pdev->dev.coherent_dma_mask = ~0;
|
||||
|
||||
platform_device_register(pdev);
|
||||
}
|
||||
|
||||
|
||||
void xhci_setup(Services *services)
|
||||
{
|
||||
module_dwc3_driver_init();
|
||||
module_xhci_plat_init();
|
||||
|
||||
arndale_xhci_init(services->env);
|
||||
|
||||
/* setup DWC3-controller platform device */
|
||||
platform_device *pdev = (platform_device *)kzalloc(sizeof(platform_device), 0);
|
||||
pdev->name = (char *)"dwc3";
|
||||
pdev->id = 0;
|
||||
pdev->num_resources = 2;
|
||||
pdev->resource = _dwc3;
|
||||
|
||||
/*needed for DMA buffer allocation. See 'hcd_buffer_alloc' in 'buffer.c' */
|
||||
static u64 dma_mask = ~(u64)0;
|
||||
pdev->dev.dma_mask = &dma_mask;
|
||||
pdev->dev.coherent_dma_mask = ~0;
|
||||
|
||||
platform_device_register(pdev);
|
||||
}
|
||||
|
||||
|
||||
void platform_hcd_init(Genode::Env &, Services *services)
|
||||
{
|
||||
ehci_setup(services);
|
||||
xhci_setup(services);
|
||||
}
|
||||
1
src/drivers/usb_host/spec/arndale/regulator/consts.h
Normal file
1
src/drivers/usb_host/spec/arndale/regulator/consts.h
Normal file
@@ -0,0 +1 @@
|
||||
#include <spec/exynos5/regulator/consts.h>
|
||||
30
src/drivers/usb_host/spec/arndale/target.mk
Normal file
30
src/drivers/usb_host/spec/arndale/target.mk
Normal file
@@ -0,0 +1,30 @@
|
||||
DDE_LINUX_DIR = $(BASE_DIR)/../dde_linux
|
||||
|
||||
include $(DDE_LINUX_DIR)/src/drivers/usb_host/target.inc
|
||||
|
||||
TARGET = arndale_usb_host_drv
|
||||
REQUIRES = arm_v7
|
||||
|
||||
INC_DIR += $(DDE_LINUX_DIR)/src/drivers/usb_host
|
||||
INC_DIR += $(DDE_LINUX_DIR)/src/include
|
||||
INC_DIR += $(DDE_LINUX_DIR)/src/drivers/usb_host/spec/arm
|
||||
INC_DIR += $(DDE_LINUX_DIR)/src/include/spec/arm
|
||||
INC_DIR += $(DDE_LINUX_DIR)/src/include/spec/arm_v7
|
||||
|
||||
SRC_CC += spec/arm/platform.cc
|
||||
SRC_CC += spec/arndale/platform.cc
|
||||
|
||||
SRC_C += usb/dwc3/core.c
|
||||
SRC_C += usb/dwc3/dwc3-exynos.c
|
||||
SRC_C += usb/dwc3/host.c
|
||||
SRC_C += usb/host/ehci-exynos.c
|
||||
SRC_C += usb/host/xhci-plat.c
|
||||
|
||||
CC_OPT += -DCONFIG_USB_EHCI_TT_NEWSCHED=1
|
||||
CC_OPT += -DCONFIG_USB_DWC3_HOST=1
|
||||
CC_OPT += -DCONFIG_USB_OTG_UTILS=1
|
||||
CC_OPT += -DCONFIG_USB_XHCI_PLATFORM=1
|
||||
CC_OPT += -DDWC3_QUIRK
|
||||
|
||||
vpath %.cc $(DDE_LINUX_DIR)/src
|
||||
vpath % $(DDE_LINUX_DIR)/src/drivers/usb_host
|
||||
35
src/include/hw/spec/arm/arndale_board.h
Normal file
35
src/include/hw/spec/arm/arndale_board.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* \brief Arndale specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-15
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_
|
||||
#define _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_
|
||||
|
||||
#include <hw/uart/exynos.h>
|
||||
#include <hw/spec/arm/boot_info.h>
|
||||
#include <hw/spec/arm/cortex_a15.h>
|
||||
#include <hw/spec/arm/exynos5.h>
|
||||
|
||||
namespace Hw::Arndale_board {
|
||||
|
||||
using namespace Exynos5;
|
||||
|
||||
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
|
||||
using Serial = Genode::Exynos_uart;
|
||||
|
||||
enum {
|
||||
UART_BASE = UART_2_MMIO_BASE,
|
||||
UART_CLOCK = 100000000,
|
||||
};
|
||||
}
|
||||
|
||||
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_ */
|
||||
66
src/include/hw/spec/arm/exynos5.h
Normal file
66
src/include/hw/spec/arm/exynos5.h
Normal file
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* \brief MMIO and IRQ definitions common to Exynos5 SoC
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2013-11-25
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <drivers/defs/arm_v7.h>
|
||||
|
||||
#ifndef _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
|
||||
#define _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
|
||||
|
||||
namespace Exynos5 {
|
||||
|
||||
using namespace Arm_v7;
|
||||
|
||||
enum {
|
||||
/* normal RAM */
|
||||
RAM_0_BASE = 0x40000000,
|
||||
RAM_0_SIZE = 0x80000000,
|
||||
|
||||
/* device IO memory */
|
||||
MMIO_0_BASE = 0x10000000,
|
||||
MMIO_0_SIZE = 0x10000000,
|
||||
|
||||
/* interrupt controller */
|
||||
IRQ_CONTROLLER_BASE = 0x10480000,
|
||||
IRQ_CONTROLLER_SIZE = 0x00010000,
|
||||
IRQ_CONTROLLER_VT_CTRL_BASE = 0x10484000,
|
||||
IRQ_CONTROLLER_VT_CTRL_SIZE = 0x1000,
|
||||
IRQ_CONTROLLER_VT_CPU_BASE = 0x10486000,
|
||||
IRQ_CONTROLLER_VT_CPU_SIZE = 0x1000,
|
||||
|
||||
/* UART */
|
||||
UART_2_MMIO_BASE = 0x12C20000,
|
||||
UART_2_MMIO_SIZE = 0x1000,
|
||||
UART_2_IRQ = 85,
|
||||
|
||||
/* pulse-width-modulation timer */
|
||||
PWM_MMIO_BASE = 0x12dd0000,
|
||||
PWM_MMIO_SIZE = 0x1000,
|
||||
PWM_CLOCK = 66000000,
|
||||
PWM_IRQ_0 = 68,
|
||||
|
||||
/* multicore timer */
|
||||
MCT_MMIO_BASE = 0x101c0000,
|
||||
MCT_MMIO_SIZE = 0x1000,
|
||||
MCT_CLOCK = 24000000,
|
||||
MCT_IRQ_L0 = 152,
|
||||
MCT_IRQ_L1 = 153,
|
||||
|
||||
/* IRAM */
|
||||
IRAM_BASE = 0x02020000,
|
||||
|
||||
/* SATA/AHCI */
|
||||
SATA_IRQ = 147,
|
||||
};
|
||||
};
|
||||
|
||||
#endif /* _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_ */
|
||||
33
src/include/hw/spec/arm/odroid_xu_board.h
Normal file
33
src/include/hw/spec/arm/odroid_xu_board.h
Normal file
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* \brief Odroid XU specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-16
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_
|
||||
#define _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_
|
||||
|
||||
#include <hw/uart/exynos.h>
|
||||
#include <hw/spec/arm/boot_info.h>
|
||||
#include <hw/spec/arm/cortex_a15.h>
|
||||
#include <hw/spec/arm/exynos5.h>
|
||||
|
||||
namespace Hw::Odroid_xu_board {
|
||||
using namespace Exynos5;
|
||||
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
|
||||
using Serial = Genode::Exynos_uart;
|
||||
|
||||
enum {
|
||||
UART_BASE = UART_2_MMIO_BASE,
|
||||
UART_CLOCK = 62668800,
|
||||
};
|
||||
}
|
||||
|
||||
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_ */
|
||||
245
src/include/hw/uart/exynos.h
Normal file
245
src/include/hw/uart/exynos.h
Normal file
@@ -0,0 +1,245 @@
|
||||
/*
|
||||
* \brief Driver for the Exynos UART
|
||||
* \author Martin stein
|
||||
* \date 2013-01-09
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _INCLUDE__DRIVERS__UART__EXYNOS_H_
|
||||
#define _INCLUDE__DRIVERS__UART__EXYNOS_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <util/mmio.h>
|
||||
|
||||
namespace Genode { class Exynos_uart; }
|
||||
|
||||
|
||||
/**
|
||||
* Exynos UART driver base
|
||||
*/
|
||||
class Genode::Exynos_uart: Mmio
|
||||
{
|
||||
protected:
|
||||
|
||||
/**
|
||||
* Line control
|
||||
*/
|
||||
struct Ulcon : Register<0x0, 32>
|
||||
{
|
||||
struct Word_length : Bitfield<0, 2> { enum { _8_BIT = 3 }; };
|
||||
struct Stop_bits : Bitfield<2, 1> { enum { _1_BIT = 0 }; };
|
||||
struct Parity_mode : Bitfield<3, 3> { enum { NONE = 0 }; };
|
||||
struct Infrared_mode : Bitfield<6, 1> { };
|
||||
|
||||
/**
|
||||
* Initialization value
|
||||
*/
|
||||
static access_t init_value()
|
||||
{
|
||||
return Word_length::bits(Word_length::_8_BIT) |
|
||||
Stop_bits::bits(Stop_bits::_1_BIT) |
|
||||
Parity_mode::bits(Parity_mode::NONE) |
|
||||
Infrared_mode::bits(0);
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* Control
|
||||
*/
|
||||
struct Ucon : Register<0x4, 32>
|
||||
{
|
||||
struct Receive_mode : Bitfield<0, 2> { enum { IRQ_POLL = 1 }; };
|
||||
struct Transmit_mode : Bitfield<2, 2> { enum { IRQ_POLL = 1 }; };
|
||||
struct Send_brk_signal : Bitfield<4, 1> { };
|
||||
struct Loop_back_mode : Bitfield<5, 1> { };
|
||||
struct Rx_err_irq : Bitfield<6, 1> { };
|
||||
struct Rx_timeout : Bitfield<7, 1> { };
|
||||
struct Rx_irq_type : Bitfield<8, 1> { enum { LEVEL = 1 }; };
|
||||
struct Tx_irq_type : Bitfield<9, 1> { enum { LEVEL = 1 }; };
|
||||
struct Rx_to_dma_susp : Bitfield<10, 1> { };
|
||||
struct Rx_to_empty_rx : Bitfield<11, 1> { };
|
||||
struct Rx_to_interval : Bitfield<12, 4> { };
|
||||
struct Rx_dma_bst_size : Bitfield<16, 3> { };
|
||||
struct Tx_dma_bst_size : Bitfield<20, 3> { };
|
||||
|
||||
/**
|
||||
* Initialization value
|
||||
*/
|
||||
static access_t init_value()
|
||||
{
|
||||
return Receive_mode::bits(Receive_mode::IRQ_POLL) |
|
||||
Transmit_mode::bits(Transmit_mode::IRQ_POLL) |
|
||||
Rx_timeout::bits(1);
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* FIFO control
|
||||
*/
|
||||
struct Ufcon : Register<0x8, 32>
|
||||
{
|
||||
struct Fifo_en : Bitfield<0, 1> { };
|
||||
struct Rx_fifo_rst : Bitfield<1, 1> { };
|
||||
struct Tx_fifo_rst : Bitfield<2, 1> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Modem control
|
||||
*/
|
||||
struct Umcon : Register<0xc, 32>
|
||||
{
|
||||
struct Send_request : Bitfield<0, 1> { };
|
||||
struct Modem_irq : Bitfield<3, 1> { };
|
||||
struct Auto_flow_ctl : Bitfield<4, 1> { };
|
||||
struct Rts_trigger : Bitfield<5, 3> { };
|
||||
|
||||
/**
|
||||
* Initialization value
|
||||
*/
|
||||
static access_t init_value()
|
||||
{
|
||||
return Send_request::bits(0) |
|
||||
Modem_irq::bits(0) |
|
||||
Auto_flow_ctl::bits(0) |
|
||||
Rts_trigger::bits(0);
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* FIFO status
|
||||
*/
|
||||
struct Ufstat : Register<0x18, 32>
|
||||
{
|
||||
struct Rx_fifo_count : Bitfield<0, 8> { };
|
||||
struct Rx_fifo_full : Bitfield<8, 1> { };
|
||||
struct Tx_fifo_full : Bitfield<24, 1> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Transmit buffer
|
||||
*/
|
||||
struct Utxh : Register<0x20, 32>
|
||||
{
|
||||
struct Transmit_data : Bitfield<0, 8> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Receive buffer
|
||||
*/
|
||||
struct Urxh : Register<0x24, 32>
|
||||
{
|
||||
struct Receive_data : Bitfield<0, 8> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Baud Rate Divisor
|
||||
*/
|
||||
struct Ubrdiv : Register<0x28, 32>
|
||||
{
|
||||
struct Baud_rate_div : Bitfield<0, 16> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Fractional part of Baud Rate Divisor
|
||||
*/
|
||||
struct Ufracval : Register<0x2c, 32>
|
||||
{
|
||||
struct Baud_rate_frac : Bitfield<0, 4> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Interrupt mask register
|
||||
*/
|
||||
template <unsigned OFF>
|
||||
struct Uintx : Register<OFF, 32>
|
||||
{
|
||||
struct Rxd : Register<OFF, 32>::template Bitfield<0, 1> { };
|
||||
struct Error : Register<OFF, 32>::template Bitfield<1, 1> { };
|
||||
struct Txd : Register<OFF, 32>::template Bitfield<2, 1> { };
|
||||
struct Modem : Register<OFF, 32>::template Bitfield<3, 1> { };
|
||||
};
|
||||
|
||||
using Uintp = Uintx<0x30>;
|
||||
using Uintm = Uintx<0x38>;
|
||||
|
||||
void _rx_enable()
|
||||
{
|
||||
write<Ufcon::Fifo_en>(1);
|
||||
|
||||
/* mask all IRQs except receive IRQ */
|
||||
write<Uintm>(Uintm::Error::bits(1) |
|
||||
Uintm::Txd::bits(1) |
|
||||
Uintm::Modem::bits(1));
|
||||
|
||||
/* clear pending IRQs */
|
||||
write<Uintp>(Uintp::Rxd::bits(1) |
|
||||
Uintp::Error::bits(1) |
|
||||
Uintp::Txd::bits(1) |
|
||||
Uintp::Modem::bits(1));
|
||||
}
|
||||
|
||||
bool _rx_avail() {
|
||||
return (read<Ufstat>() & (Ufstat::Rx_fifo_count::bits(0xff)
|
||||
| Ufstat::Rx_fifo_full::bits(1))); }
|
||||
|
||||
/**
|
||||
* Return character received via UART
|
||||
*/
|
||||
char _rx_char()
|
||||
{
|
||||
(void)read<Ufcon>();
|
||||
char c = read<Urxh::Receive_data>();
|
||||
|
||||
/* clear pending RX IRQ */
|
||||
write<Uintp>(Uintp::Rxd::bits(1));
|
||||
return c;
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Constructor
|
||||
*
|
||||
* \param base MMIO base address
|
||||
* \param clock reference clock
|
||||
* \param baud_rate targeted baud rate
|
||||
*/
|
||||
Exynos_uart(addr_t const base, unsigned const clock,
|
||||
unsigned const baud_rate) : Mmio(base)
|
||||
{
|
||||
/* RX and TX FIFO reset */
|
||||
write<Ufcon::Rx_fifo_rst>(1);
|
||||
write<Ufcon::Tx_fifo_rst>(1);
|
||||
while (read<Ufcon::Rx_fifo_rst>() || read<Ufcon::Tx_fifo_rst>()) ;
|
||||
|
||||
/* init control registers */
|
||||
write<Ulcon>(Ulcon::init_value());
|
||||
write<Ucon>(Ucon::init_value());
|
||||
write<Umcon>(Umcon::init_value());
|
||||
|
||||
/* apply baud rate */
|
||||
float const div_val = ((float)clock / (baud_rate * 16)) - 1;
|
||||
Ubrdiv::access_t const ubrdiv = div_val;
|
||||
Ufracval::access_t const ufracval =
|
||||
((float)div_val - ubrdiv) * 16;
|
||||
write<Ubrdiv::Baud_rate_div>(ubrdiv);
|
||||
write<Ufracval::Baud_rate_frac>(ufracval);
|
||||
}
|
||||
|
||||
/**
|
||||
* Print character 'c' through the UART
|
||||
*/
|
||||
void put_char(char const c)
|
||||
{
|
||||
while (read<Ufstat::Tx_fifo_full>()) ;
|
||||
write<Utxh::Transmit_data>(c);
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _INCLUDE__DRIVERS__UART__EXYNOS_H_ */
|
||||
@@ -2,7 +2,9 @@ source [genode_dir]/tool/run/boot_dir/hw
|
||||
|
||||
|
||||
proc bootstrap_link_address { } {
|
||||
if {[have_spec "panda"]} { return "0x88000000" }
|
||||
if {[have_spec "arndale"]} { return "0x88000000" }
|
||||
if {[have_spec "odroid_xu"]} { return "0x88000000" }
|
||||
if {[have_spec "panda"]} { return "0x88000000" }
|
||||
|
||||
puts "unknown platform no linker address known"
|
||||
exit -1
|
||||
@@ -14,7 +16,9 @@ proc bootstrap_link_address { } {
|
||||
#
|
||||
proc base_src { } {
|
||||
|
||||
if {[have_spec panda]} { return base-hw-panda }
|
||||
if {[have_spec arndale]} { return base-hw-arndale }
|
||||
if {[have_spec odroid_xu]} { return base-hw-odroid_xu }
|
||||
if {[have_spec panda]} { return base-hw-panda }
|
||||
|
||||
global specs
|
||||
|
||||
|
||||
Reference in New Issue
Block a user