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zynq: add SMP support for Zynq-7000 boards

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This commit is contained in:
Johannes Schlatow
2018-01-11 16:54:43 +01:00
committed by Norman Feske
parent cdc389ef3d
commit 47faf8c4f8
12 changed files with 16 additions and 148 deletions
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6
lib/mk/spec/zynq_parallella/bootstrap-hw.mk
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@@ -8,13 +8,13 @@ SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/zynq_parallella/platform.cc
SRC_CC += bootstrap/spec/zynq/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
NR_OF_CPUS = 1
NR_OF_CPUS = 2
vpath bootstrap/spec/zynq_parallella/platform.cc $(REP_DIR)/src/
vpath bootstrap/spec/zynq/platform.cc $(BASE_HW_DIR)/src/
include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc

2
lib/mk/spec/zynq_parallella/core-hw.mk
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@@ -10,7 +10,7 @@ BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_parallella
NR_OF_CPUS = 1
NR_OF_CPUS = 2
# include less specific configuration
include $(BASE_HW_DIR)/lib/mk/spec/zynq/core-hw.inc

6
lib/mk/spec/zynq_zc702/bootstrap-hw.mk
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@@ -8,13 +8,13 @@ SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/zynq_zc702/platform.cc
SRC_CC += bootstrap/spec/zynq/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
NR_OF_CPUS = 1
NR_OF_CPUS = 2
vpath bootstrap/spec/zynq_zc702/platform.cc $(REP_DIR)/src/
vpath bootstrap/spec/zynq/platform.cc $(BASE_HW_DIR)/src/
include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc

2
lib/mk/spec/zynq_zc702/core-hw.mk
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@@ -10,7 +10,7 @@ BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc702
NR_OF_CPUS = 1
NR_OF_CPUS = 2
# include less specific configuration
include $(BASE_HW_DIR)/lib/mk/spec/zynq/core-hw.inc

6
lib/mk/spec/zynq_zc706/bootstrap-hw.mk
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@@ -8,13 +8,13 @@ SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/zynq_zc706/platform.cc
SRC_CC += bootstrap/spec/zynq/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
NR_OF_CPUS = 1
NR_OF_CPUS = 2
vpath bootstrap/spec/zynq_zc706/platform.cc $(REP_DIR)/src/
vpath bootstrap/spec/zynq/platform.cc $(BASE_HW_DIR)/src/
include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc

2
lib/mk/spec/zynq_zc706/core-hw.mk
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@@ -10,7 +10,7 @@ BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc706
NR_OF_CPUS = 1
NR_OF_CPUS = 2
# include less specific configuration
include $(BASE_HW_DIR)/lib/mk/spec/zynq/core-hw.inc

6
lib/mk/spec/zynq_zedboard/bootstrap-hw.mk
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@@ -8,13 +8,13 @@ SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/zynq_zedboard/platform.cc
SRC_CC += bootstrap/spec/zynq/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
NR_OF_CPUS = 1
NR_OF_CPUS = 2
vpath bootstrap/spec/zynq_zedboard/platform.cc $(REP_DIR)/src/
vpath bootstrap/spec/zynq/platform.cc $(BASE_HW_DIR)/src/
include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc

2
lib/mk/spec/zynq_zedboard/core-hw.mk
View File

@@ -10,7 +10,7 @@ BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zedboard
NR_OF_CPUS = 1
NR_OF_CPUS = 2
# include less specific configuration
include $(BASE_HW_DIR)/lib/mk/spec/zynq/core-hw.inc

33
src/bootstrap/spec/zynq_parallella/platform.cc
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@@ -1,33 +0,0 @@
/*
* \brief Platform implementations specific for base-hw and Zynq
* \author Johannes Schlatow
* \author Stefan Kalkowski
* \date 2014-12-15
*/
/*
* Copyright (C) 2014-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* core includes */
#include <platform.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
RAM_0_SIZE - 0x1000 }),
late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
CORTEX_A9_PRIVATE_MEM_SIZE },
Memory_region { UART_1_MMIO_BASE,
UART_SIZE },
Memory_region { PL310_MMIO_BASE,
PL310_MMIO_SIZE }) { }
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
return false; }

33
src/bootstrap/spec/zynq_zc702/platform.cc
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@@ -1,33 +0,0 @@
/*
* \brief Platform implementations specific for base-hw and Zynq
* \author Johannes Schlatow
* \author Stefan Kalkowski
* \date 2014-12-15
*/
/*
* Copyright (C) 2014-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* core includes */
#include <platform.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
RAM_0_SIZE - 0x1000 }),
late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
CORTEX_A9_PRIVATE_MEM_SIZE },
Memory_region { UART_1_MMIO_BASE,
UART_SIZE },
Memory_region { PL310_MMIO_BASE,
PL310_MMIO_SIZE }) { }
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
return false; }

33
src/bootstrap/spec/zynq_zc706/platform.cc
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@@ -1,33 +0,0 @@
/*
* \brief Platform implementations specific for base-hw and Zynq
* \author Johannes Schlatow
* \author Stefan Kalkowski
* \date 2014-12-15
*/
/*
* Copyright (C) 2014-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* core includes */
#include <platform.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
RAM_0_SIZE - 0x1000 }),
late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
CORTEX_A9_PRIVATE_MEM_SIZE },
Memory_region { UART_1_MMIO_BASE,
UART_SIZE },
Memory_region { PL310_MMIO_BASE,
PL310_MMIO_SIZE }) { }
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
return false; }

33
src/bootstrap/spec/zynq_zedboard/platform.cc
View File

@@ -1,33 +0,0 @@
/*
* \brief Platform implementations specific for base-hw and Zynq
* \author Johannes Schlatow
* \author Stefan Kalkowski
* \date 2014-12-15
*/
/*
* Copyright (C) 2014-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* core includes */
#include <platform.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
RAM_0_SIZE - 0x1000 }),
late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
CORTEX_A9_PRIVATE_MEM_SIZE },
Memory_region { UART_1_MMIO_BASE,
UART_SIZE },
Memory_region { PL310_MMIO_BASE,
PL310_MMIO_SIZE }) { }
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
return false; }