Add support for Nvidia Jetson TK1

kernel/fiasco/src/kern/arm/bsp/tegra/Kconfig

@@ -1,6 +1,5 @@
 # PF: TEGRA
 # PFDESCR: NVIDIA Tegra platform
-# PFSELECT: CAN_ARM_CPU_CORTEX_A9 CAN_ARM_CACHE_L2CXX0
 # PFDEPENDS: ARM
 
 choice
@@ -10,10 +9,19 @@ choice
 config PF_TEGRA2
 	bool "Tegra2"
 	depends on PF_TEGRA
+	select CAN_ARM_CPU_CORTEX_A9
+	select CAN_ARM_CACHE_L2CXX0
 
 config PF_TEGRA3
 	bool "Tegra3"
 	depends on PF_TEGRA
+	select CAN_ARM_CPU_CORTEX_A9
+	select CAN_ARM_CACHE_L2CXX0
+
+config PF_TEGRAK1
+	bool "TegraK1"
+	depends on PF_TEGRA
+	select CAN_ARM_CPU_CORTEX_A15
 
 endchoice
 

kernel/fiasco/src/kern/arm/bsp/tegra/Modules

@@ -3,8 +3,9 @@
 PREPROCESS_PARTS        += 16550 pic_gic generic_tickless_idle libuart
 PREPROCESS_PARTS-$(CONFIG_PF_TEGRA_TIMER_MP)  += mptimer
 PREPROCESS_PARTS-$(CONFIG_PF_TEGRA_TIMER_TMR) += tegra_timer_tmr
-RAM_PHYS_BASE-$(CONFIG_PF_TEGRA2) := $(if $(CONFIG_ARM_EM_TZ),0x30000000,0x0)
-RAM_PHYS_BASE-$(CONFIG_PF_TEGRA3) := $(if $(CONFIG_ARM_EM_TZ),0xa0000000,0x80000000)
+RAM_PHYS_BASE-$(CONFIG_PF_TEGRA2)  := $(if $(CONFIG_ARM_EM_TZ),0x30000000,0x0)
+RAM_PHYS_BASE-$(CONFIG_PF_TEGRA3)  := $(if $(CONFIG_ARM_EM_TZ),0xa0000000,0x80000000)
+RAM_PHYS_BASE-$(CONFIG_PF_TEGRAK1) := 0x80000000
 RAM_PHYS_BASE                     := $(RAM_PHYS_BASE-y)
 INTERFACES_KERNEL       += gic
 MPCORE_PHYS_BASE        := 0x50040000

kernel/fiasco/src/kern/arm/bsp/tegra/config-arm-tegra.cpp

@@ -5,3 +5,7 @@ INTERFACE[arm && pf_tegra2]:
 INTERFACE[arm && pf_tegra3]:
 
 #define TARGET_NAME "Tegra3"
+
+INTERFACE[arm && pf_tegrak1]:
+
+#define TARGET_NAME "TegraK1"

kernel/fiasco/src/kern/arm/bsp/tegra/mem_layout-arm-tegra.cpp

@@ -1,4 +1,4 @@
-INTERFACE [arm && pf_tegra]:
+INTERFACE [arm && !pf_tegrak1]:
 
 EXTENSION class Mem_layout
 {
@@ -18,3 +18,24 @@ public:
     Pmc_phys_base         = 0x7000e400,
   };
 };
+
+INTERFACE [arm && pf_tegrak1]:
+
+EXTENSION class Mem_layout
+{
+public:
+  enum Phys_layout_tegra : Address
+  {
+    Mp_scu_phys_base      = 0x50040000,
+    L2cxx0_phys_base      = 0x50043000,
+
+    Gic_cpu_phys_base     = 0x50042000,
+    Gic_dist_phys_base    = 0x50041000,
+    Gic2_cpu_phys_base    = 0x50020000,
+    Gic2_dist_phys_base   = 0x50021000,
+
+    Tmr_phys_base         = 0x60005000,
+    Clock_reset_phys_base = 0x60006000,
+    Pmc_phys_base         = 0x7000e400,
+  };
+};