10 Commits
r56 ... r40

Author SHA1 Message Date
Sebastian Sumpf
7a22db7c38 FOC/L4RE: Add license 2013-08-09 12:22:43 +02:00
Sebastian Sumpf
e720764a9b Sigma0: raise sigma0's priority to maximum.
When sigma0 runs on a lower priority than the rest of the threads in the system
it might come to the point that while answering a page fault or I/O memory area
request the timeslice of the caller (core-pager) gets fully consumed. As long as
other threads are still executable and don't block sigma0 won't do progress
anymore, because it runs at the lowest priority.  This commit simply sets
sigma0's priority to the highest in the system.

Was: 'sigma0_prio.patch'
2013-01-11 17:48:18 +01:00
Sebastian Sumpf
3cae95ac84 Fiasco.OC: fix io-port fault answer in sigma0
In sigma0 normally no answer tag to a request/fault is created. It
simply uses the message tag received with the request. This doesn't work out
when I/O ports are requested. This patch constructs an appropriate answer tag.
Moreover, we have to enable I/O port protection in the kernel configuration.

Was: 'sigma0_ioport.patch'
2013-01-11 17:48:18 +01:00
Sebastian Sumpf
9f2115ee41 JBD: Increase name buffer to 32K
Increase the size of the JDB kernel object names buffer. The original size was
too small for some Genode scenarios and caused missing thread names in the
kernel debugger thread list.

Was: 'jdb_kobject_names.patch'
2013-01-11 17:48:18 +01:00
Sebastian Sumpf
a6b127594f i.MX53 support
Was: 'imx53_support.patch'
2013-01-11 17:48:18 +01:00
Sebastian Sumpf
10d7926ce0 X86: Single stepping
This patch enables the user land to use the CPU's single stepping mode on
x86_32 platforms. It is needed to enable the use of GDB monitor for
user-level debugging.

Was: 'foc_single_step_x86.patch'
2013-01-11 17:48:18 +01:00
Sebastian Sumpf
c9830dbc1e Ex_regs: Change 'user_flags'
Return true if thread is ready.

Was: 'foc_exregs_ret_state.patch'
2013-01-11 17:48:17 +01:00
Sebastian Sumpf
2e9923b4fd Caps: fix l4_task_cap_equal semantic.
The syscall l4_task_cap_equal almost returns false although the referenced
kernel-objects are equal. This patch changes the semantic of the syscall so that
whenever two capabilities refering the same kernel-object are compared it will
return true. Please refer to the discussion of the following mail thread:
http://www.mail-archive.com/l4-hackers@os.inf.tu-dresden.de/msg05162.html

Was 'foc_caps_equal.patch'
2013-01-11 17:47:48 +01:00
Sebastian Sumpf
5a3d8fa28f ARM: Errata 743622
Restrict the appliance of ERRATA 743622 to CPU revisions: r2p0-r2p2.

Was 'foc_arm_errata.patch'
2013-01-11 17:12:32 +01:00
Sebastian Sumpf
3e974d6ccd GDB monitor: Check for ARM breakpoint IP
Performed in 'slow_trapentry'. Was 'fix_exception_ip.patch'.
2013-01-11 17:09:06 +01:00
26 changed files with 529 additions and 19 deletions

349
COPYING-GPL-2 Normal file
View File

@@ -0,0 +1,349 @@
NOTE! This License shall not affect user programs that use the micro-kernel
API to invoke kernel-operations or services provided in other address
spaces - this is merely considered normal use of the kernel or
accompanying user-level services, and does not fall under the heading of
"derivative work".
-----------------------------------------------------------------------
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Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
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You should also get your employer (if you work as a programmer) or your
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Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.

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@@ -685,6 +685,14 @@ config POWERSAVE_GETCHAR
prevent some P4 processors from being overheated. This option
requires a working timer IRQ to wakeup getchar periodically.
config USER_SINGLE_STEP
bool "Enable user level single stepping support"
depends on IA32
default n
help
This option enables single stepping of user level applications outside of
JDB.
choice
prompt "Warn levels"
default WARN_WARNING

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@@ -43,7 +43,7 @@ IMPLEMENTATION:
enum
{
Name_buffer_size = 8192,
Name_buffer_size = 4*8192,
Name_entries = Name_buffer_size / sizeof(Jdb_kobject_name),
};

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@@ -25,6 +25,13 @@ config PF_IMX_51
help
Choose for i.MX51
config PF_IMX_53
bool "i.MX53"
depends on PF_IMX
select CAN_ARM_CPU_CORTEX_A8
help
Choose for i.MX53
endchoice
config PF_IMX_RAM_PHYS_BASE
@@ -32,3 +39,4 @@ config PF_IMX_RAM_PHYS_BASE
default 0xc0000000 if PF_IMX_21
default 0x80000000 if PF_IMX_35
default 0x90000000 if PF_IMX_51
default 0x70000000 if PF_IMX_53

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@@ -7,9 +7,12 @@ PREPROCESS_PARTS += $(if $(CONFIG_PF_IMX_21),imx21 kern_start_0xd)
PREPROCESS_PARTS += $(if $(CONFIG_PF_IMX_35),imx35 imx_epit)
PREPROCESS_PARTS += $(if $(CONFIG_PF_IMX_51),imx51 imx_epit \
pic_gic pic_gic_mxc_tzic)
PREPROCESS_PARTS += $(if $(CONFIG_PF_IMX_53),imx53 imx_epit \
pic_gic pic_gic_mxc_tzic)
CONFIG_KERNEL_LOAD_ADDR := $(CONFIG_PF_IMX_RAM_PHYS_BASE)
INTERFACES_KERNEL += $(if $(CONFIG_PF_IMX_51),gic)
INTERFACES_KERNEL += $(if $(CONFIG_PF_IMX_53),gic)
uart_IMPL += uart-imx
config_IMPL += config-arm-imx
@@ -17,10 +20,12 @@ mem_layout_IMPL += mem_layout-arm-imx
pic_IMPL += $(if $(CONFIG_PF_IMX_21),pic-arm-imx)
pic_IMPL += $(if $(CONFIG_PF_IMX_35),pic-arm-imx)
pic_IMPL += $(if $(CONFIG_PF_IMX_51),pic-gic pic-arm-imx51)
pic_IMPL += $(if $(CONFIG_PF_IMX_53),pic-gic pic-arm-imx51)
bootstrap_IMPL += bootstrap-arm-imx
timer_IMPL += $(if $(CONFIG_PF_IMX_21),timer-arm-imx21)
timer_IMPL += $(if $(CONFIG_PF_IMX_35),timer-arm-imx_epit)
timer_IMPL += $(if $(CONFIG_PF_IMX_51),timer-arm-imx_epit)
timer_IMPL += $(if $(CONFIG_PF_IMX_53),timer-arm-imx_epit)
timer_tick_IMPL += timer_tick-single-vector
kernel_uart_IMPL += kernel_uart-arm-imx
reset_IMPL += reset-arm-imx

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@@ -25,7 +25,7 @@ map_hw(void *pd)
}
//-----------------------------------------------------------------------------
IMPLEMENTATION [arm && imx51]:
IMPLEMENTATION [arm && (imx51 || imx53)]:
void
map_hw(void *pd)
{

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@@ -9,3 +9,7 @@ INTERFACE [arm && imx35]:
INTERFACE [arm && imx51]:
#define TARGET_NAME "i.MX51"
INTERFACE [arm && imx53]:
#define TARGET_NAME "i.MX53"

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@@ -90,3 +90,29 @@ public:
Gic_dist_phys_base = 0xe0000000,
};
};
INTERFACE [arm && imx && imx53]: // ---------------------------------------
EXTENSION class Mem_layout
{
public:
enum Virt_layout_imx53 {
Timer_map_base = 0xef1ac000,
Uart_map_base = 0xef1bc000,
Watchdog_map_base = 0xef198000,
Gic_cpu_map_base = 0,
Gic_dist_map_base = 0xef2fc000,
Uart_base = Uart_map_base,
};
enum Phys_layout_imx53 {
Device_phys_base_1 = 0x53f00000,
Device_phys_base_2 = 0x0ff00000,
Watchdog_phys_base = 0x53f98000, // wdog1
Timer_phys_base = 0x53fac000, // epit1
Uart_phys_base = 0x53fbc000, // uart1
Gic_dist_phys_base = 0x0fffc000,
};
};

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@@ -1,9 +1,9 @@
INTERFACE [arm && pic_gic && imx51]:
INTERFACE [arm && pic_gic && (imx51 || imx53)]:
#include "gic.h"
// ------------------------------------------------------------------------
IMPLEMENTATION [arm && pic_gic && imx51]:
IMPLEMENTATION [arm && pic_gic && (imx51 || imx53)]:
#include "irq_mgr_multi_chip.h"
#include "kmem.h"

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@@ -25,7 +25,7 @@ platform_reset(void)
}
// ------------------------------------------------------------------------
IMPLEMENTATION [arm && (imx35 || imx51)]:
IMPLEMENTATION [arm && (imx35 || imx51 || imx53)]:
#include "io.h"
#include "kmem.h"

View File

@@ -39,7 +39,7 @@ public:
};
INTERFACE [arm && imx51]: // ----------------------------------------------
INTERFACE [arm && (imx51 || imx53)]: // ----------------------------------------------
EXTENSION class Timer
{

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@@ -25,7 +25,7 @@ IMPLEMENT L4::Uart *Uart::uart()
return &uart;
}
IMPLEMENTATION [imx51]:
IMPLEMENTATION [imx51 || imx53]:
#include "uart_imx.h"
@@ -37,7 +37,7 @@ IMPLEMENT L4::Uart *Uart::uart()
return &uart;
}
IMPLEMENTATION [imx21 || imx35 || imx51]:
IMPLEMENTATION [imx21 || imx35 || imx51 || imx53]:
#include "mem_layout.h"

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@@ -428,7 +428,13 @@ PRIVATE static inline
void Cpu::init_errata_workarounds() {}
//---------------------------------------------------------------------------
IMPLEMENTATION [arm && armv6plus]:
IMPLEMENTATION [arm && armv6plus && omap4_pandaboard]:
PRIVATE static inline
void Cpu::init_errata_workarounds() {}
//---------------------------------------------------------------------------
IMPLEMENTATION [arm && armv6plus && !omap4_pandaboard]:
PRIVATE static inline
void
@@ -494,8 +500,8 @@ Cpu::init_errata_workarounds()
if (rev == 0x20 || rev == 0x21 || rev == 0x22)
set_c15_c0_1((1 << 12) | (1 << 22));
// errata: 743622
if ((rev & 0xf0) == 0x20)
// errata: 743622 (r2p0 - r2p2)
if ((rev & 0xf0) == 0x20 && (rev & 0xf) < 0x3)
set_c15_c0_1(1 << 6);
// errata: 751472
@@ -505,6 +511,9 @@ Cpu::init_errata_workarounds()
}
}
//---------------------------------------------------------------------------
IMPLEMENTATION [arm && armv6plus]:
IMPLEMENT
void
Cpu::id_init()

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@@ -303,6 +303,10 @@ extern "C" {
if (handle_copro_fault[copro](opcode, ts))
return;
}
/* check for ARM default GDB breakpoint */
if (!(ts->psr & Proc::Status_thumb) && opcode == 0xe7ffdefe)
ts->pc -= 4;
}
undef_insn:
@@ -402,7 +406,7 @@ Thread::user_ip() const
IMPLEMENT inline
Mword
Thread::user_flags() const
{ return 0; }
{ return state() & Thread_ready; }
IMPLEMENT inline NEEDS[Thread::exception_triggered]
void
@@ -590,6 +594,10 @@ Thread::condition_valid(Unsigned32 insn, Unsigned32 psr)
return (v[insn >> 28] >> (psr >> 28)) & 1;
}
IMPLEMENT inline
void Thread::user_single_step(bool)
{}
// ------------------------------------------------------------------------
IMPLEMENTATION [arm && armv6plus]:

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@@ -46,6 +46,30 @@
jmp slowtraps
.endm
#ifdef CONFIG_USER_SINGLE_STEP
.macro HANDLE_USER_TRAP1
/* Save EFLAGS, this may trap if user task had single stepping activated
* test for single stepping
*/
pushf
addl $4, %esp
testl $EFLAGS_TF, -4(%esp)
.endm
.macro RESTORE_USER_TRAP1
/* Restore single stepping if it has been set */
je 1f
orl $EFLAGS_TF, (%esp)
1:
.endm
#else
.macro HANDLE_USER_TRAP1
.endm
.macro RESTORE_USER_TRAP1
.endm
#endif
.p2align 4
.globl entry_vec01_debug
entry_vec01_debug:
@@ -59,6 +83,15 @@ entry_vec01_debug:
cmpl $entry_sys_fast_ipc_log, (%esp)
je 2f
#endif
/* test if trap was raised within kernel */
testl $3, 4(%esp)
jne 1f
/* turn of EFLAGS.TF */
btrl $7, 8(%esp)
iret
1: pushl $0
pushl $1
pusha
@@ -227,11 +260,17 @@ alien_sys_fast_ipc_log:
.p2align(4)
.global entry_sys_fast_ipc_c
entry_sys_fast_ipc_c:
HANDLE_USER_TRAP1
pop %esp
pushl $(GDT_DATA_USER|SEL_PL_U) /* user ss */
pushl %ebp // push user SP (get in ebp)
// Fake user eflags, set IOPL to 3
pushl $(EFLAGS_IOPL_U | EFLAGS_IF)
RESTORE_USER_TRAP1
cld
// Fake user cs. This cs value is never used with exception
// that the thread is ex_regs'd before we leave with sysexit.

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@@ -86,6 +86,12 @@ public:
// static const bool hlt_works_ok = false;
static bool hlt_works_ok;
#ifdef CONFIG_USER_SINGLE_STEP
static const bool user_single_step = true;
#else
static const bool user_single_step = false;
#endif
// the default uart to use for serial console
static const unsigned default_console_uart = 1;
static const unsigned default_console_uart_baudrate = 115200;

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@@ -93,7 +93,7 @@ Thread::user_ip() const
IMPLEMENT inline
Mword
Thread::user_flags() const
{ return regs()->flags(); }
{ return state() & Thread_ready; }
/** Check if the pagefault occured at a special place: At some places in the
kernel we want to ensure that a specific address is mapped. The regular
@@ -189,6 +189,10 @@ Thread::handle_slow_trap(Trap_state *ts)
goto generic_debug;
}
if (Config::user_single_step && ts->_trapno == 1 && from_user)
if (send_exception(ts))
goto success;
if (from_user && _space.user_mode())
{
if (ts->_trapno == 14 && Kmem::is_io_bitmap_page_fault(ts->_cr2))
@@ -438,7 +442,8 @@ Thread::send_exception_arch(Trap_state *ts)
// thread (not alien) and it's a debug trap,
// debug traps for aliens are always reflected as exception IPCs
if (!(state() & Thread_alien)
&& (ts->_trapno == 1 || ts->_trapno == 3))
&& ((ts->_trapno == 1 && !Config::user_single_step)
|| ts->_trapno == 3))
return 0; // we do not handle this
if (ts->_trapno == 3)
@@ -491,6 +496,11 @@ Thread::user_ip(Mword ip)
}
}
IMPLEMENT inline
void
Thread::user_single_step(bool)
{}
//----------------------------------------------------------------------------
IMPLEMENTATION [(ia32,amd64,ux) && !io]:
@@ -819,3 +829,16 @@ PRIVATE static inline
int
Thread::call_nested_trap_handler(Trap_state *)
{ return -1; }
//---------------------------------------------------------------------------
IMPLEMENTATION [ia32]:
IMPLEMENT inline
void
Thread::user_single_step(bool enable)
{
if (!Config::user_single_step)
return;
regs()->flags(enable ? user_flags() | EFLAGS_TF : user_flags() & ~EFLAGS_TF);
}

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@@ -308,6 +308,10 @@ Thread::user_ip(Mword ip)
}
}
IMPLEMENT inline
void Thread::user_single_step(bool)
{}
PUBLIC inline NEEDS ["trap_state.h"]
int
Thread::send_exception_arch(Trap_state * /*ts*/)

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@@ -488,10 +488,12 @@ Task::sys_caps_equal(Syscall_frame *, Utcb *utcb)
if (obj_a.special() || obj_b.special())
return commit_result(obj_a.special_cap() == obj_b.special_cap());
Obj_space::Capability c_a = lookup(obj_a.cap());
Obj_space::Capability c_b = lookup(obj_b.cap());
Kobject_iface* ki_a = lookup(obj_a.cap()).obj();
Kobject_iface* ki_b = lookup(obj_b.cap()).obj();
Address a_a = ki_a ? ki_a->kobject_start_addr() : 0;
Address a_b = ki_b ? ki_b->kobject_start_addr() : 0;
return commit_result(c_a == c_b);
return commit_result(a_a == a_b);
}
PRIVATE inline NOEXPORT

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@@ -72,6 +72,7 @@ public:
{
Exr_cancel = 0x10000,
Exr_trigger_exception = 0x20000,
Exr_single_step = 0x40000,
};
enum Vcpu_ctl_flags
@@ -139,6 +140,8 @@ public:
inline Mword user_flags() const;
inline void user_single_step(bool);
/** nesting level in debugger (always critical) if >1 */
static Per_cpu<unsigned long> nested_trap_recover;
static void handle_remote_requests_irq() asm ("handle_remote_cpu_requests");

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@@ -520,6 +520,8 @@ Thread_object::ex_regs(Address ip, Address sp,
if (o_ip) *o_ip = user_ip();
if (o_flags) *o_flags = user_flags();
(ops & Exr_single_step) ? user_single_step(true) : user_single_step(false);
// Changing the run state is only possible when the thread is not in
// an exception.
if (!(ops & Exr_cancel) && (state() & Thread_in_exception))

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@@ -0,0 +1,4 @@
PLATFORM_NAME = "Freescale i.MX53"
PLATFORM_ARCH = arm
PLATFORM_RAM_BASE = 0x70000000
PLATFORM_RAM_SIZE_MB = 1024

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@@ -75,6 +75,7 @@ SUPPORT_CC_arm-tegra2 := platform/tegra2.cc
SUPPORT_CC_arm-imx21 := platform/imx.cc
SUPPORT_CC_arm-imx35 := platform/imx.cc
SUPPORT_CC_arm-imx51 := platform/imx.cc
SUPPORT_CC_arm-imx53 := platform/imx.cc
SUPPORT_CC_arm-om := platform/om.cc
SUPPORT_CC_arm-kirkwood := platform/kirkwood.cc
DEFAULT_RELOC_arm-imx21 := 0x00200000 # because of blob

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@@ -36,6 +36,9 @@ class Platform_arm_imx : public Platform_single_region_ram
#elif defined(PLATFORM_TYPE_imx51)
static L4::Io_register_block_mmio r(0x73fbc000);
static L4::Uart_imx51 _uart;
#elif defined(PLATFORM_TYPE_imx53)
static L4::Io_register_block_mmio r(0x53fbc000);
static L4::Uart_imx51 _uart;
#else
#error Which platform type?
#endif

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@@ -27,6 +27,7 @@
#include "ioports.h"
#include "mem_man_test.h"
#include <l4/sys/debugger.h>
#include <l4/sys/scheduler.h>
/* started as the L4 sigma0 task from crt0.S */
@@ -61,6 +62,10 @@ init(l4_kernel_info_t *info)
l4_debugger_set_object_name(L4_BASE_FACTORY_CAP, "root factory");
l4_debugger_set_object_name(L4_BASE_THREAD_CAP, "sigma0");
l4_sched_param_t params = l4_sched_param(255);
l4_scheduler_run_thread(L4_BASE_SCHEDULER_CAP, L4_BASE_THREAD_CAP, &params);
Page_alloc_base::init();
init_memory(info);

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@@ -39,8 +39,9 @@ void handle_io_page_fault(l4_umword_t t, l4_utcb_t *utcb, Answer *a)
size = l4_fpage_size(fp) + PORT_SHIFT;
unsigned long i = io_ports.alloc(Region::bs(port, 1UL << size, t));
if (i == port)
if (i == port) {
a->snd_fpage(l4_iofpage(port >> PORT_SHIFT, size - PORT_SHIFT));
else
a->tag = l4_msgtag(0, 0, 1, 0);
} else
a->error(L4_ENOMEM);
}