alex/foc
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

FOC: Fix cache line size for Cortex A15

Browse Source 
Added errata 774769, also there is no need to clean the cache on page table
update.
This commit is contained in:
Sebastian Sumpf
2013-03-04 11:12:57 +01:00
parent 78f10a6283
commit b1bffcdba8
4 changed files with 51 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
kernel/fiasco/src/drivers/arm/mmu-arm.cpp
View File

@@ -1,4 +1,4 @@
INTERFACE:
INTERFACE[arm && !armca15]:
#include "mem.h"
#include "std_macros.h"
@@ -18,6 +18,29 @@ public:
};
};
//---------------------------------------------------------------------------
INTERFACE[arm && armca15]:
#include "mem.h"
#include "std_macros.h"
EXTENSION class Mmu
{
public:
static void btc_flush();
static void btc_inv();
enum
{
Cache_line_size = 64,
Cache_line_mask = Cache_line_size - 1,
Icache_line_size = 64,
Icache_line_mask = Icache_line_size - 1,
};
};
//---------------------------------------------------------------------------
IMPLEMENTATION [arm && armv5]:
@@ -344,7 +367,7 @@ EXTENSION class Mmu
};
//-----------------------------------------------------------------------------
INTERFACE [arm && (armca9 || armca15)]:
INTERFACE [arm && armca9]:
EXTENSION class Mmu
{
@@ -361,6 +384,24 @@ EXTENSION class Mmu
};
//-----------------------------------------------------------------------------
INTERFACE [arm && armca15]:
EXTENSION class Mmu
{
enum
{
SET_SIZE_32KB = 1 << 13,
SET_SIZE = SET_SIZE_32KB,
SET_INCR = 1 << 6,
WAY_INCR = 1 << 31,
WAY_SIZE = 2,
};
};
//-----------------------------------------
IMPLEMENTATION [arm && (armca8 || armca9 || armca15)]:

2
kernel/fiasco/src/kern/arm/bsp/exynos5/Modules
View File

@@ -2,7 +2,7 @@
SUBSYSTEMS += LIBUART
OBJECTS_LIBUART += uart_s3c2410.o
PREPROCESS_PARTS += exynos5 libuart
PREPROCESS_PARTS += exynos5 libuart arm_cpu_errata
PREPROCESS_PARTS += $(if $(CONFIG_PF_EXYNOS5_ARNDALE), exynos5_arndale pic_gic)
CONFIG_KERNEL_LOAD_ADDR := 0x40000000

5
kernel/fiasco/src/kern/arm/cpu-arm.cpp
View File

@@ -616,6 +616,11 @@ Cpu::init_errata_workarounds()
if (rev < 0x30)
set_c15_c0_1(1 << 11);
}
// errata: 774769 (must be done in secure mode)
if (part == 0xc0f)
{
clear_actrl(0x1 << 25);
}
}
}

4
kernel/fiasco/src/kern/arm/pagetable-arch.cpp
View File

@@ -137,7 +137,7 @@ Pte::need_cache_clean()
}
//---------------------------------------------------------------------------
IMPLEMENTATION [arm && !vcache && !armca9]:
IMPLEMENTATION [arm && !vcache && !armca9 && !armca15]:
PUBLIC static inline
bool
@@ -147,7 +147,7 @@ Pte::need_cache_clean()
}
//---------------------------------------------------------------------------
IMPLEMENTATION [arm && !vcache && armca9]:
IMPLEMENTATION [arm && !vcache && (armca9 || armca15)]:
PUBLIC static inline
bool