FOC: Arndale single core support

Stage2, GIC, timer, UART, FPU running on single core.

kernel/fiasco/src/kern/arm/bsp/exynos5/Modules

@@ -3,16 +3,18 @@
 SUBSYSTEMS       += LIBUART
 OBJECTS_LIBUART  += uart_s3c2410.o
 PREPROCESS_PARTS += exynos5 libuart
-PREPROCESS_PARTS += $(if $(CONFIG_PF_EXYNOS5_ARNDALE), exynos5_arndale)
+PREPROCESS_PARTS += $(if $(CONFIG_PF_EXYNOS5_ARNDALE), exynos5_arndale pic_gic)
 
 CONFIG_KERNEL_LOAD_ADDR := 0x40000000
 
+INTERFACES_KERNEL+= $(if $(CONFIG_PF_EXYNOS5_ARNDALE),gic)
+
 bootstrap_IMPL   += bootstrap-arm-exynos5
 clock_IMPL       += clock-generic
 config_IMPL      += config-arm-exynos5
 kernel_uart_IMPL += kernel_uart-arm-exynos5
 mem_layout_IMPL  += mem_layout-arm-exynos5
-pic_IMPL         += pic-arm-gic-exynos5
+pic_IMPL         += pic-gic pic-arm-gic-exynos5
 reset_IMPL       += reset-arm-exynos5
 timer_IMPL       += timer-arm-exynos5
 timer_tick_IMPL  += timer_tick-single-vector

kernel/fiasco/src/kern/arm/bsp/exynos5/bootstrap-arm-exynos5.cpp

@@ -14,4 +14,6 @@ map_hw(void *pd)
 {
   map_dev<Mem_layout::Devices1_phys_base>(pd, 1);
   map_dev<Mem_layout::Devices2_phys_base>(pd, 2);
+  map_dev<Mem_layout::Devices3_phys_base>(pd, 3);
+  map_dev<Mem_layout::Devices4_phys_base>(pd, 4);
 }

kernel/fiasco/src/kern/arm/bsp/exynos5/mem_layout-arm-exynos5.cpp

@@ -6,6 +6,8 @@ public:
   enum  Phys_layout_exynos5 : Address {
     Devices1_phys_base = 0x10000000,
     Devices2_phys_base = 0x12c00000,
+    Devices3_phys_base = 0x10400000,
+    Devices4_phys_base = 0x12d00000,
   };
 
   enum Virt_layout_exynos5 : Address {
@@ -19,8 +21,11 @@ EXTENSION class Mem_layout
 {
 public:
   enum Virt_layout_exynos5_arndale : Address {
-    Uart_base       = Uart2_map_base,
-    Sdram_phys_base = 0x40000000,
+    Uart_base         = Uart2_map_base,
+    Sdram_phys_base   = 0x40000000,
+    Gic_cpu_map_base  = Devices3_map_base + 0x82000,
+    Gic_dist_map_base = Devices3_map_base + 0x81000,
+    Timer_map_base    = Devices4_map_base + 0xd0000,
   };
 };
 

kernel/fiasco/src/kern/arm/bsp/exynos5/pic-arm-gic-exynos5.cpp

@@ -1,14 +1,24 @@
-IMPLEMENTATION [arm && exynos5]:
+INTERFACE [arm && pic_gic exynos5]:
 
-#include "panic.h"
-#include "warn.h"
-#include "initcalls.h"
+#include "gic.h"
+
+IMPLEMENTATION [arm && pic_gic exynos5]:
+
+#include "irq_mgr_multi_chip.h"
+#include "kmem.h"
 
 IMPLEMENT FIASCO_INIT
 void
 Pic::init()
 {
-  NOT_IMPL_PANIC;
+  typedef Irq_mgr_multi_chip<8> M;
+
+  M *m = new Boot_object<M>(16);
+
+  gic.construct(Kmem::Gic_cpu_map_base, Kmem::Gic_dist_map_base);
+  m->add_chip(0, gic, gic->nr_irqs());
+
+  Irq_mgr::mgr = m;
 }
 
 IMPLEMENT inline
@@ -19,8 +29,3 @@ IMPLEMENT inline
 void Pic::restore_all(Status)
 {}
 
-extern "C"
-void irq_handler()
-{
-	NOT_IMPL_PANIC;
-}

kernel/fiasco/src/kern/arm/bsp/exynos5/timer-arm-exynos5.cpp

@@ -1,14 +1,28 @@
 INTERFACE [arm & exynos5]:
 
+#include "kmem.h"
+
 EXTENSION class Timer
 {
-  public:
-    static unsigned irq() { return  64; /* timer0 */ }
+public:
+  enum {
+    BASE = Kmem::Timer_map_base,
+    CFG0      = BASE,
+    CFG1      = BASE + 0x4,
+    TCON      = BASE + 0x8,
+    TCNTB0    = BASE + 0xc,
+    TCMPB0    = BASE + 0x10,
+    TINT_STAT = BASE + 0x44,
+    ONE_MS    = 33000, /* HZ */
+  };
+
+    static unsigned irq() { return  68; /* timer0 */ }
 };
 
 IMPLEMENTATION [arm && exynos5]:
 
-#include "warn.h"
+#include "mmu.h"
+#include "io.h"
 
 IMPLEMENT inline
 void
@@ -21,19 +35,35 @@ Timer::update_one_shot(Unsigned64 wakeup)
 IMPLEMENT
 void Timer::init(unsigned)
 {
-//	NOT_IMPL_PANIC;
+  /* prescaler to one */
+  Io::write<Mword>(0x1, CFG0);
+  /* divider to 1 */
+  Io::write<Mword>(0x0, CFG1);
+
+  /* program 1ms */
+  Io::write<Mword>(ONE_MS, TCNTB0);
+  Io::write<Mword>(0x0, TCMPB0);
+
+  /* enable IRQ */
+  Io::write<Mword>(0x1, TINT_STAT);
+
+  /* load and start timer in invterval mode*/
+  Io::write<Mword>(0xa, TCON);
+  Io::write<Mword>(0x9, TCON);
 }
 
-IMPLEMENT inline NEEDS["warn.h"]
+IMPLEMENT inline NEEDS["config.h", "kip.h"]
 Unsigned64
 Timer::system_clock()
 {
-	NOT_IMPL_PANIC;
-  return 0;
+  if (Config::Scheduler_one_shot)
+    return 0;
+  else
+    return Kip::k()->clock;
 }
 
-PUBLIC static inline NEEDS["warn.h"]
+PUBLIC static inline NEEDS["io.h"]
 void Timer::acknowledge()
 {
-	NOT_IMPL_PANIC;
+  Io::set<Mword>(0x20, TINT_STAT);
 }

kernel/fiasco/src/kern/arm/bsp/exynos5/uart-arm-exynos5.cpp

@@ -1,6 +1,6 @@
 IMPLEMENTATION [arm && exynos5]: // ------------------------------
 
-IMPLEMENT int Uart::irq() const { return 32 + 54; }
+IMPLEMENT int Uart::irq() const { return 32 + 53; }
 
 IMPLEMENTATION: // --------------------------------------------------------
 

kernel/fiasco/src/kern/arm/bsp/exynos5/warn-exynos5.cpp

@@ -2,4 +2,4 @@ INTERFACE [exynos5]:
 #include "panic.h"
 
 #define NOT_IMPL WARN "%s not implemented", __PRETTY_FUNCTION__
-#define NOT_IMPL_PANIC panic("%s not implemented\n", __PRETTY_FUNCTION__);
+#define NOT_IMPL_PANIC panic("%s not implemented (from %p)\n", __PRETTY_FUNCTION__, __builtin_return_address((0)));

kernel/fiasco/src/kern/arm/fpu-arm.cpp

@@ -78,6 +78,7 @@ Fpu::copro_enable()
                "mcr  p15, 0, %0, c1, c0, 2\n"
                : : "r" (0), "I" (0x00f00000));
   Mem::dsb();
+  Mem::isb();
 }
 
 // ------------------------------------------------------------------------

kernel/fiasco/src/kern/arm/startup-arm.cpp

@@ -65,4 +65,5 @@ Startup::stage2()
   Timer::init(0);
   Kern_lib_page::init();
   Utcb_init::init();
+  puts("Startup::stage2 finished");
 }