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FOC: Don't set SCU enable bit on Cortex-A15

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... since the SCU-control register does not exist (resverved area on Cortex-A15).
Setting this bit leads to second-level translation table faults on CPU1.
This commit is contained in:
Sebastian Sumpf
2013-08-13 12:34:55 +02:00
parent 82f255fff2
commit 14ef3a3a2b
1 changed files with 1 additions and 1 deletions
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kernel/fiasco/src/kern/arm/tramp-mp.S
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@@ -59,7 +59,7 @@ _tramp_mp_entry:
msr cpsr_c, r0
// enable SMP
#ifndef CONFIG_ARM_EM_NS
#if !defined(CONFIG_ARM_EM_NS) && !defined(CONFIG_ARM_CORTEX_A15)
adr r0, .Lmpcore_phys_base
ldr r0, [r0]
ldr r1, [r0]