From 14ef3a3a2b8555bed2b48cf62d3cd06cb5e6e8a9 Mon Sep 17 00:00:00 2001 From: Sebastian Sumpf Date: Tue, 13 Aug 2013 12:34:55 +0200 Subject: [PATCH] FOC: Don't set SCU enable bit on Cortex-A15 ... since the SCU-control register does not exist (resverved area on Cortex-A15). Setting this bit leads to second-level translation table faults on CPU1. --- kernel/fiasco/src/kern/arm/tramp-mp.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/fiasco/src/kern/arm/tramp-mp.S b/kernel/fiasco/src/kern/arm/tramp-mp.S index e4cb4bc0..b33505fd 100644 --- a/kernel/fiasco/src/kern/arm/tramp-mp.S +++ b/kernel/fiasco/src/kern/arm/tramp-mp.S @@ -59,7 +59,7 @@ _tramp_mp_entry: msr cpsr_c, r0 // enable SMP -#ifndef CONFIG_ARM_EM_NS +#if !defined(CONFIG_ARM_EM_NS) && !defined(CONFIG_ARM_CORTEX_A15) adr r0, .Lmpcore_phys_base ldr r0, [r0] ldr r1, [r0]