202333c881
We cannot count on the correct initialization of the diagnostic register of the secondary cores. But the boot core gets initialized by the bootchain, so we can copy over those values. Fix #3639
327 lines
9.2 KiB
C++
327 lines
9.2 KiB
C++
/*
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* \brief CPU definitions for ARM
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* \author Stefan Kalkowski
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* \date 2017-02-02
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__LIB__HW__SPEC__ARM__CPU_H_
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#define _SRC__LIB__HW__SPEC__ARM__CPU_H_
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#include <hw/spec/arm/register_macros.h>
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namespace Hw { struct Arm_cpu; }
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struct Hw::Arm_cpu
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{
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/***************************************
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** System Coprocessor 15 Definitions **
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***************************************/
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/* Main ID Register */
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ARM_CP15_REGISTER_32BIT(Midr, c0, c0, 0, 0);
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/* Cache Type Register */
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ARM_CP15_REGISTER_32BIT(Ctr, c0, c0, 0, 1);
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/* Multiprocessor Affinity Register */
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ARM_CP15_REGISTER_32BIT(Mpidr, c0, c0, 0, 5,
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struct Aff_0 : Bitfield<0, 8> { }; /* affinity value 0 */
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struct Me : Bitfield<31, 1> { }; /* multiprocessing extension */
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);
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/* System Control Register */
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ARM_CP15_REGISTER_32BIT(Sctlr, c1, c0, 0, 0,
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struct M : Bitfield<0,1> { }; /* enable MMU */
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struct A : Bitfield<1,1> { }; /* enable alignment checks */
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struct C : Bitfield<2,1> { }; /* enable data cache */
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struct I : Bitfield<12,1> { }; /* enable instruction caches */
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struct Z : Bitfield<11,1> { }; /* enable program flow prediction */
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struct V : Bitfield<13,1> { }; /* select exception entry */
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);
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/* Auxiliary Control Register */
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ARM_CP15_REGISTER_32BIT(Actlr, c1, c0, 0, 1);
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/* Coprocessor Access Control Register */
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ARM_CP15_REGISTER_32BIT(Cpacr, c1, c0, 0, 2,
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struct Cp10 : Bitfield<20, 2> { };
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struct Cp11 : Bitfield<22, 2> { };
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);
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/* Hyp System Control Register */
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ARM_CP15_REGISTER_32BIT(Hsctlr, c1, c0, 4, 0);
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/* Secure Configuration Register */
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ARM_CP15_REGISTER_32BIT(Scr, c1, c1, 0, 0,
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struct Ns : Bitfield<0, 1> { }; /* not secure */
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struct Fw : Bitfield<4, 1> { }; /* F bit writeable */
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struct Aw : Bitfield<5, 1> { }; /* A bit writeable */
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struct Scd : Bitfield<7, 1> { }; /* smc call disable */
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struct Hce : Bitfield<8, 1> { }; /* hyp call enable */
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struct Sif : Bitfield<9, 1> { }; /* secure instruction fetch */
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);
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/* Secure Debug Enable Register */
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ARM_CP15_REGISTER_32BIT(Sder, c1, c1, 0, 1);
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/* Non-Secure Access Control Register */
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ARM_CP15_REGISTER_32BIT(Nsacr, c1, c1, 0, 2,
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struct Cpnsae10 : Bitfield<10, 1> { }; /* Co-processor 10 access */
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struct Cpnsae11 : Bitfield<11, 1> { }; /* Co-processor 11 access */
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struct Ns_smp : Bitfield<18,1> { };
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);
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/* Hyp Coprocessor Trap Register */
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ARM_CP15_REGISTER_32BIT(Hcptr, c1, c1, 4, 2,
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template <unsigned N> struct Tcp : Bitfield<N, 1> {};
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struct Tase : Bitfield<15, 1> { };
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struct Tta : Bitfield<20, 1> { };
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struct Tcpac : Bitfield<31, 1> { };
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);
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/**
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* Common translation table base register
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*/
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struct Ttbr : Genode::Register<32>
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{
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enum Memory_region { CACHEABLE = 1 };
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struct C : Bitfield<0,1> { }; /* inner cacheable */
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struct S : Bitfield<1,1> { }; /* shareable */
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struct Rgn : Bitfield<3,2> { }; /* outer cachable mode */
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struct Nos : Bitfield<5,1> { }; /* not outer shareable */
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struct Ba : Bitfield<14, 18> { }; /* translation table base */
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/*********************************
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* Multiprocessing Extensions **
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*********************************/
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struct Irgn_1 : Bitfield<0,1> { };
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struct Irgn_0 : Bitfield<6,1> { };
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struct Irgn : Genode::Bitset_2<Irgn_0, Irgn_1> { }; /* inner cache mode */
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static access_t init(Genode::addr_t table)
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{
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access_t v = Ttbr::Ba::masked(table);
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Ttbr::Rgn::set(v, Ttbr::CACHEABLE);
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if (Mpidr::Me::get(Mpidr::read())) { /* check for SMP system */
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Ttbr::Irgn::set(v, Ttbr::CACHEABLE);
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Ttbr::S::set(v, 1);
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} else
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Ttbr::C::set(v, 1);
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return v;
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};
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};
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struct Ttbr_64bit : Genode::Register<64>
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{
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struct Ba : Bitfield<4, 35> { }; /* translation table base */
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struct Asid : Bitfield<48,8> { };
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};
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/* Translation Table Base Control Register */
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ARM_CP15_REGISTER_32BIT(Ttbcr, c2, c0, 0, 2,
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/***************************************
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** Large Physical Address Extensions **
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***************************************/
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struct T0sz : Bitfield<0, 3> { };
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struct Irgn0 : Bitfield<8, 2> { };
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struct Orgn0 : Bitfield<10, 2> { };
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struct Sh0 : Bitfield<12, 2> { };
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struct T1sz : Bitfield<16, 3> { };
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struct Irgn1 : Bitfield<24, 2> { };
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struct Orgn1 : Bitfield<26, 2> { };
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struct Sh1 : Bitfield<28, 2> { };
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struct Eae : Bitfield<31, 1> { }; /* extended address enable */
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);
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/* Translation Table Base Register 0 */
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ARM_CP15_REGISTER_32BIT(Ttbr0, c2, c0, 0, 0);
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ARM_CP15_REGISTER_64BIT(Ttbr0_64bit, c2, 0);
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/* Translation Table Base Register 1 */
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ARM_CP15_REGISTER_32BIT(Ttbr1, c2, c0, 0, 1);
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ARM_CP15_REGISTER_64BIT(Ttbr1_64bit, c2, 1);
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/* Hyp Translation Control Register */
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ARM_CP15_REGISTER_32BIT(Htcr, c2, c0, 4, 2);
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/* Hyp Translation Table Base Register */
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ARM_CP15_REGISTER_64BIT(Httbr_64bit, c2, 4);
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/* Virtualization Translation Control Register */
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ARM_CP15_REGISTER_32BIT(Vtcr, c2, c1, 4, 2,
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struct Sl0 : Bitfield<6,2> {}; /* starting level for table walks */
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);
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/* Domain Access Control Register */
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ARM_CP15_REGISTER_32BIT(Dacr, c3, c0, 0, 0,
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struct D0 : Bitfield<0,2> { }; /* access mode for domain 0 */
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);
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/**
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* Common fault status register
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*/
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struct Fsr : Genode::Register<32>
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{
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struct Fs_0 : Bitfield<0, 4> { };
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struct Fs_1 : Bitfield<10, 1> { };
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struct Fs : Genode::Bitset_2<Fs_0, Fs_1> { }; /* fault status */
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};
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/* Data Fault Status Register */
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ARM_CP15_REGISTER_32BIT(Dfsr, c5, c0, 0, 0,
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struct Wnr : Bitfield<11, 1> { }; /* write not read bit */
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);
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/* Instruction Fault Status Register */
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ARM_CP15_REGISTER_32BIT(Ifsr, c5, c0, 0, 1);
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/* Data Fault Address Register */
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ARM_CP15_REGISTER_32BIT(Dfar, c6, c0, 0, 0);
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/* Instruction Fault Address Register */
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ARM_CP15_REGISTER_32BIT(Ifar, c6, c0, 0, 2);
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/* Invalidate instruction cache line by MVA to PoU */
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ARM_CP15_REGISTER_32BIT(Icimvau, c7, c5, 0, 1);
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/* Branch predictor invalidate all */
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ARM_CP15_REGISTER_32BIT(Bpiall, c7, c5, 0, 6);
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/* Data Cache Clean and Invalidate by MVA to PoC */
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ARM_CP15_REGISTER_32BIT(Dccimvac, c7, c14, 0, 1);
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/* Invalidate entire unified TLB */
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ARM_CP15_REGISTER_32BIT(Tlbiall, c8, c7, 0, 0);
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/* Invalidate entire unified TLB (inner-shareable) */
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ARM_CP15_REGISTER_32BIT(Tlbiallis, c8, c3, 0, 0);
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/* Invalidate unified TLB by ASID */
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ARM_CP15_REGISTER_32BIT(Tlbiasid, c8, c7, 0, 2);
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/* Invalidate unified TLB by ASID (inner-shareable) */
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ARM_CP15_REGISTER_32BIT(Tlbiasidis, c8, c3, 0, 2);
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/* Memory Attribute Indirection Register 0 */
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ARM_CP15_REGISTER_32BIT(Mair0, c10, c2, 0, 0,
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struct Attr0 : Bitfield<0, 8> { };
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struct Attr1 : Bitfield<8, 8> { };
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struct Attr2 : Bitfield<16, 8> { };
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struct Attr3 : Bitfield<24, 8> { };
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);
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/* Hyp Memory Attribute Indirection Register 0 */
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ARM_CP15_REGISTER_32BIT(Hmair0, c10, c2, 4, 0);
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/* Monitor Vector Base Address Register */
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ARM_CP15_REGISTER_32BIT(Mvbar, c12, c0, 0, 1);
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/* Hyp Vector Base Address Register */
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ARM_CP15_REGISTER_32BIT(Hvbar, c12, c0, 4, 0);
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/* Context ID Register */
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ARM_CP15_REGISTER_32BIT(Cidr, c13, c0, 0, 1);
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/* Counter Frequency register */
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ARM_CP15_REGISTER_32BIT(Cntfrq, c14, c0, 0, 0);
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/* Physical Timer Value register */
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ARM_CP15_REGISTER_32BIT(Cntp_tval, c14, c2, 0, 0);
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/* Physical Timer Control register */
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ARM_CP15_REGISTER_32BIT(Cntp_ctl, c14, c2, 0, 1,
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struct Enable : Bitfield<0, 1> {};
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struct Istatus : Bitfield<2, 1> {};
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);
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/* Physical Count register */
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ARM_CP15_REGISTER_64BIT(Cntpct, c14, 0);
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/* Diagnostic register */
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ARM_CP15_REGISTER_32BIT(Diag, c15, c0, 0, 1);
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/******************************
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** Program status registers **
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******************************/
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/**
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* Common program status register
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*/
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struct Psr : Genode::Register<32>
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{
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/*
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* CPU mode
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*/
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struct M : Bitfield<0,5>
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{
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enum {
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USR = 16,
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SVC = 19,
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MON = 22,
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HYP = 26,
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SYS = 31,
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};
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};
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struct F : Bitfield<6,1> { }; /* FIQ disable */
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struct I : Bitfield<7,1> { }; /* IRQ disable */
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struct A : Bitfield<8,1> { }; /* async. abort disable */
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};
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ARM_BANKED_REGISTER(Cpsr, cpsr);
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/**********************************
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** Cache maintainance functions **
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**********************************/
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static inline void synchronization_barrier()
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{
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asm volatile("dsb\n"
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"isb\n");
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}
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static inline void wait_for_xchg(volatile void * addr,
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unsigned long new_value,
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unsigned long expected_value)
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{
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asm volatile(
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/* check if load value of 'addr' is as expected */
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"1: ldrex r7, [%0] \n"
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"cmp r7, %2 \n"
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/* if not, wait for other CPU to send us an event */
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"wfene \n"
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/* if yes, attempt to write 'new_value' to 'addr' */
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"strexeq r7, %1, [%0] \n"
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/* if write failed, restart */
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"cmpeq r7, #0 \n"
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"bne 1b \n"
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"dmb \n"
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:: "r"(addr), "r"(new_value), "r"(expected_value) : "cc", "r7");
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}
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static inline void wakeup_waiting_cpus()
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{
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asm volatile(
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"dsb \n"
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"sev \n"
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);
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}
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};
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#endif /* _SRC__LIB__HW__SPEC__ARM__CPU_H_ */
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