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core: unify handling of boot modules

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Instead of solving the problem to deliver ROM modules to core while booting
differently for the several kernels (multi-boot, elfweaver, core re-linking),
this commit unifies the approaches. It always builds core as a library, and
after all binaries are built from a run-script, the run-tool will link an
ELF image out of the core-library and all boot modules. Thereby, core can
access its ROM modules directly.

This approach now works for all kernels except Linux.

With this solution, there is no [build_dir]/bin/core binary available anymore.
For debugging purposes you will find a core binary without boot modules, but
with debug symbols under [run_dir].core.

Fix #2095
This commit is contained in:
Stefan Kalkowski
2016-09-15 16:08:33 +02:00
committed by Christian Helmuth
parent 340a18007c
commit 7e1692d997
80 changed files with 450 additions and 1395 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
repos/base-fiasco/src/core/target.inc → repos/base-fiasco/lib/mk/core.inc
View File

@@ -1,5 +1,3 @@
TARGET = core
GEN_CORE_DIR = $(BASE_DIR)/src/core
SRC_CC += stack_area.cc \
@@ -19,7 +17,6 @@ SRC_CC += stack_area.cc \
io_port_session_support.cc \
irq_session_component.cc \
main.cc \
multiboot_info.cc \
pager.cc \
pager_ep.cc \
pager_object.cc \
@@ -50,7 +47,6 @@ LIBS += base-common
include $(GEN_CORE_DIR)/version.inc
vpath main.cc $(GEN_CORE_DIR)
vpath multiboot_info.cc $(GEN_CORE_DIR)
vpath ram_session_component.cc $(GEN_CORE_DIR)
vpath rom_session_component.cc $(GEN_CORE_DIR)
vpath cap_session_component.cc $(GEN_CORE_DIR)

4
repos/base-fiasco/src/core/spec/x86/target.mk → repos/base-fiasco/lib/mk/spec/x86/core.mk
View File

@@ -1,4 +1,4 @@
include $(PRG_DIR)/../../target.inc
include $(REP_DIR)/lib/mk/core.inc
REQUIRES += x86
SRC_CC += platform_x86.cc
@@ -6,4 +6,4 @@ SRC_CC += platform_x86.cc
vpath io_port_session_component.cc $(GEN_CORE_DIR)/spec/x86
vpath io_port_session_support.cc $(GEN_CORE_DIR)/spec/x86
vpath platform_services.cc $(GEN_CORE_DIR)/spec/x86
vpath platform_x86.cc $(REP_DIR)/src/core/spec/x86

5
repos/base-fiasco/mk/spec/fiasco_x86.mk
View File

@@ -11,11 +11,6 @@ SPECS += pci ps2 vesa framebuffer
L4_INC_DIR += $(L4_BUILD_DIR)/include/x86/l4v2 \
$(L4_BUILD_DIR)/include/x86
#
# Linker options that are specific for x86
#
LD_TEXT_ADDR ?= 0x01000000
#
# Also include less-specific configuration last
#

4
repos/base-fiasco/src/core/include/platform.h
View File

@@ -21,7 +21,7 @@
#include "platform_generic.h"
#include "platform_thread.h"
#include "platform_pd.h"
#include "multiboot.h"
#include "boot_modules.h"
namespace Genode {
@@ -42,7 +42,6 @@ namespace Genode {
Phys_allocator _io_port_alloc; /* I/O port allocator */
Phys_allocator _irq_alloc; /* IRQ allocator */
Phys_allocator _region_alloc; /* virtual memory allocator for core */
Multiboot_info _mb_info; /* multiboot information */
Rom_fs _rom_fs; /* ROM file system */
Rom_module _kip_rom; /* ROM module for Fiasco KIP */
@@ -59,7 +58,6 @@ namespace Genode {
*
* - Map and provide KIP as ROM module
* - Initializes region allocator
* - Initializes multiboot info structure
*/
void _setup_basics();

41
repos/base-fiasco/src/core/platform.cc
View File

@@ -30,7 +30,6 @@
#include <platform_thread.h>
#include <platform_pd.h>
#include <util.h>
#include <multiboot.h>
/* Fiasco includes */
namespace Fiasco {
@@ -364,10 +363,6 @@ void Platform::_setup_basics()
_kip_rom = Rom_module((addr_t)kip, L4_PAGESIZE, "l4v2_kip");
_rom_fs.insert(&_kip_rom);
/* update multi-boot info pointer from KIP */
addr_t mb_info_addr = kip->user_ptr;
log("MBI @ ", Hex(mb_info_addr));
/* parse memory descriptors - look for virtual memory configuration */
/* XXX we support only one VM region (here and also inside RM) */
using L4::Kip::Mem_desc;
@@ -398,11 +393,9 @@ void Platform::_setup_basics()
/* FIXME if the kernel helps to find out max address - use info here */
_io_mem_alloc.add_range(0, ~0);
/* remove KIP and MBI area from region and IO_MEM allocator */
/* remove KIP area from region and IO_MEM allocator */
remove_region(Region((addr_t)kip, (addr_t)kip + L4_PAGESIZE), _region_alloc);
remove_region(Region((addr_t)kip, (addr_t)kip + L4_PAGESIZE), _io_mem_alloc);
remove_region(Region(mb_info_addr, mb_info_addr + _mb_info.size()), _region_alloc);
remove_region(Region(mb_info_addr, mb_info_addr + _mb_info.size()), _io_mem_alloc);
/* remove core program image memory from region and IO_MEM allocator */
addr_t img_start = (addr_t) &_prog_img_beg;
@@ -417,29 +410,12 @@ void Platform::_setup_basics()
void Platform::_setup_rom()
{
Rom_module rom;
for (unsigned i = FIRST_ROM; i < _mb_info.num_modules(); i++) {
if (!(rom = _mb_info.get_module(i)).valid()) continue;
Rom_module *new_rom = new(core_mem_alloc()) Rom_module(rom);
_rom_fs.insert(new_rom);
log(" mod[", i, "] ",
Hex_range<addr_t>(new_rom->addr(), new_rom->size()), " ",
new_rom->name());
/* zero remainder of last ROM page */
size_t count = L4_PAGESIZE - rom.size() % L4_PAGESIZE;
if (count != L4_PAGESIZE)
memset(reinterpret_cast<void *>(rom.addr() + rom.size()), 0, count);
/* remove ROM area from region and IO_MEM allocator */
remove_region(Region(new_rom->addr(), new_rom->addr() + new_rom->size()), _region_alloc);
remove_region(Region(new_rom->addr(), new_rom->addr() + new_rom->size()), _io_mem_alloc);
/* add area to core-accessible ranges */
add_region(Region(new_rom->addr(), new_rom->addr() + new_rom->size()), _core_address_ranges());
/* add boot modules to ROM FS */
Boot_modules_header * header = &_boot_modules_headers_begin;
for (; header < &_boot_modules_headers_end; header++) {
Rom_module * rom = new (core_mem_alloc())
Rom_module(header->base, header->size, (const char*)header->name);
_rom_fs.insert(rom);
}
}
@@ -447,8 +423,7 @@ void Platform::_setup_rom()
Platform::Platform() :
_ram_alloc(nullptr), _io_mem_alloc(core_mem_alloc()),
_io_port_alloc(core_mem_alloc()), _irq_alloc(core_mem_alloc()),
_region_alloc(core_mem_alloc()),
_mb_info(get_kip()->user_ptr, true)
_region_alloc(core_mem_alloc())
{
/*
* We must be single-threaded at this stage and so this is safe.