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hw: basic support for ODROID XU board (Fix #991)

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This commit is contained in:
Stefan Kalkowski
2013-12-03 11:10:13 +01:00
committed by Norman Feske
parent 9b456fb3be
commit 7b49dbf2f3
17 changed files with 266 additions and 31 deletions
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14
base/include/drivers/uart/arndale_uart_base.h → base/include/drivers/uart/exynos_uart_base.h
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@@ -1,5 +1,5 @@
/*
* \brief Driver base for the Arndale UART
* \brief Driver base for the Exynos UART
* \author Martin stein
* \date 2013-01-09
*/
@@ -11,8 +11,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__DRIVERS__UART__ARNDALE_UART_BASE_H_
#define _INCLUDE__DRIVERS__UART__ARNDALE_UART_BASE_H_
#ifndef _INCLUDE__DRIVERS__UART__EXYNOS_UART_BASE_H_
#define _INCLUDE__DRIVERS__UART__EXYNOS_UART_BASE_H_
/* Genode includes */
#include <util/mmio.h>
@@ -20,9 +20,9 @@
namespace Genode
{
/**
* Arndale UART driver base
* Exynos UART driver base
*/
class Arndale_uart_base : Mmio
class Exynos_uart_base : Mmio
{
/**
* Line control
@@ -173,7 +173,7 @@ namespace Genode
* \param clock reference clock
* \param baud_rate targeted baud rate
*/
Arndale_uart_base(addr_t const base, unsigned const clock,
Exynos_uart_base(addr_t const base, unsigned const clock,
unsigned const baud_rate) : Mmio(base)
{
/* init control registers */
@@ -202,5 +202,5 @@ namespace Genode
};
}
#endif /* _INCLUDE__DRIVERS__UART__ARNDALE_UART_BASE_H_ */
#endif /* _INCLUDE__DRIVERS__UART__EXYNOS_UART_BASE_H_ */

63
base/include/platform/odroid_xu/drivers/board_base.h Normal file
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@@ -0,0 +1,63 @@
/*
* \brief Driver base for the Odroid XU board
* \author Stefan Kalkowski
* \date 2013-11-25
*/
/*
* Copyright (C) 2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__DRIVERS__BOARD_BASE_H_
namespace Genode
{
/**
* Board driver base
*/
struct Board_base
{
enum
{
/* normal RAM */
RAM_0_BASE = 0x40000000,
RAM_0_SIZE = 0x80000000,
/* device IO memory */
MMIO_0_BASE = 0x10000000,
MMIO_0_SIZE = 0x10000000,
/* interrupt controller */
GIC_CPU_MMIO_BASE = 0x10481000,
GIC_CPU_MMIO_SIZE = 0x00010000,
/* UART */
UART_2_MMIO_BASE = 0x12C20000,
UART_2_CLOCK = 62668800,
UART_2_IRQ = 85,
/* timer */
PWM_MMIO_BASE = 0x12dd0000,
PWM_MMIO_SIZE = 0x1000,
PWM_CLOCK = 66000000,
PWM_IRQ_0 = 68,
MCT_MMIO_BASE = 0x101c0000,
MCT_MMIO_SIZE = 0x1000,
MCT_CLOCK = 24000000,
MCT_IRQ_L0 = 152,
/* CPU cache */
CACHE_LINE_SIZE_LOG2 = 6,
/* wether board provides security extension */
SECURITY_EXTENSION = 0,
};
};
}
#endif /* _INCLUDE__DRIVERS__BOARD_BASE_H_ */