base: introduce caching attributes (fix #1184)

On ARM it's relevant to not only distinguish between ordinary cached memory
and write-combined one, but also having non-cached memory too. To insert the
appropriated page table entries e.g.: in the base-hw kernel, we need to preserve
the information about the kind of memory from allocation until the pager
resolves a page fault. Therefore, this commit introduces a new Cache_attribute
type, and replaces the write_combined boolean with the new type where necessary.

repos/base-foc/include/base/ipc_pager.h

@@ -16,6 +16,7 @@
 #define _INCLUDE__BASE__IPC_PAGER_H_
 
 /* Genode includes */
+#include <base/cache.h>
 #include <base/ipc.h>
 #include <base/stdint.h>
 #include <base/native_types.h>
@@ -33,12 +34,13 @@ namespace Genode {
 	{
 		private:
 
-			addr_t   _dst_addr;
-			addr_t   _src_addr;
-			bool     _write_combined;
-			unsigned _log2size;
-			bool     _rw;
-			bool     _grant;
+			addr_t          _dst_addr;
+			addr_t          _src_addr;
+			Cache_attribute _cacheability;
+			bool            _iomem;
+			unsigned        _log2size;
+			bool            _rw;
+			bool            _grant;
 
 		public:
 
@@ -46,34 +48,30 @@ namespace Genode {
 			 * Constructor
 			 */
 			Mapping(addr_t dst_addr, addr_t src_addr,
-			        bool write_combined, bool io_mem,
+			        Cache_attribute c, bool io_mem,
 			        unsigned l2size = L4_LOG2_PAGESIZE,
 			        bool rw = true, bool grant = false)
 			: _dst_addr(dst_addr), _src_addr(src_addr),
-			  _write_combined(write_combined), _log2size(l2size),
+				_cacheability(c), _iomem(io_mem), _log2size(l2size),
 			  _rw(rw), _grant(grant) { }
 
 			/**
 			 * Construct invalid flexpage
 			 */
-			Mapping() : _dst_addr(0), _src_addr(0), _write_combined(false),
-			            _log2size(0), _rw(false), _grant(false) { }
+			Mapping() : _dst_addr(0), _src_addr(0), _cacheability(UNCACHED),
+				_iomem(false), _log2size(0), _rw(false), _grant(false) { }
 
 			Fiasco::l4_umword_t dst_addr() const { return _dst_addr; }
 			bool                grant()    const { return _grant;    }
 
 			Fiasco::l4_fpage_t  fpage()    const
 			{
-				// TODO: write combined
-				//if (write_combined)
-				//	_fpage.fp.cache = Fiasco::L4_FPAGE_BUFFERABLE;
-
 				unsigned char rights = _rw ? Fiasco::L4_FPAGE_RWX : Fiasco::L4_FPAGE_RX;
 				return Fiasco::l4_fpage(_src_addr, _log2size, rights);
 			}
 
-			bool write_combined() const { return _write_combined; }
-
+			Cache_attribute cacheability() const { return _cacheability; }
+			bool iomem() { return _iomem; }
 			/**
 			 * Prepare map operation is not needed on Fiasco.OC, since we clear the
 			 * dataspace before this function is called.

repos/base-foc/src/base/ipc/pager.cc

@@ -87,12 +87,20 @@ void Ipc_pager::reply_and_wait_for_fault()
 	l4_umword_t grant   = _reply_mapping.grant() ? L4_MAP_ITEM_GRANT : 0;
 	l4_utcb_mr()->mr[0] = _reply_mapping.dst_addr() | L4_ITEM_MAP | grant;
 
-	/*
-	 * XXX Does L4_FPAGE_BUFFERABLE imply L4_FPAGE_UNCACHEABLE?
-	 */
-	if (_reply_mapping.write_combined())
+	switch (_reply_mapping.cacheability()) {
+	case WRITE_COMBINED:
 		l4_utcb_mr()->mr[0] |= L4_FPAGE_BUFFERABLE << 4;
-
+		break;
+	case CACHED:
+		l4_utcb_mr()->mr[0] |= L4_FPAGE_CACHEABLE << 4;
+		break;
+	case UNCACHED:
+		if (!_reply_mapping.iomem())
+			l4_utcb_mr()->mr[0] |= L4_FPAGE_BUFFERABLE << 4;
+		else
+			l4_utcb_mr()->mr[0] |= L4_FPAGE_UNCACHEABLE << 4;
+		break;
+	}
 	l4_utcb_mr()->mr[1] = _reply_mapping.fpage().raw;
 
 	_tag = l4_ipc_send_and_wait(_last, l4_utcb(), snd_tag,

repos/base-foc/src/core/ram_session_support.cc

@@ -29,7 +29,7 @@ void Ram_session_component::_clear_ds(Dataspace_component *ds)
 {
 	memset((void *)ds->phys_addr(), 0, ds->size());
 
-	if (ds->write_combined())
+	if (ds->cacheability() != CACHED)
 			Fiasco::l4_cache_dma_coherent(ds->phys_addr(), ds->phys_addr() + ds->size());
 }