base: introduce caching attributes (fix #1184)

On ARM it's relevant to not only distinguish between ordinary cached memory
and write-combined one, but also having non-cached memory too. To insert the
appropriated page table entries e.g.: in the base-hw kernel, we need to preserve
the information about the kind of memory from allocation until the pager
resolves a page fault. Therefore, this commit introduces a new Cache_attribute
type, and replaces the write_combined boolean with the new type where necessary.

repos/base-fiasco/include/base/ipc_pager.h

@@ -15,6 +15,7 @@
 #define _INCLUDE__BASE__IPC_PAGER_H_
 
 /* Genode includes */
+#include <base/cache.h>
 #include <base/ipc.h>
 #include <base/stdint.h>
 #include <base/native_types.h>
@@ -41,14 +42,14 @@ namespace Genode {
 			 * Constructor
 			 */
 			Mapping(addr_t dst_addr, addr_t src_addr,
-			        bool write_combined, bool io_mem,
+			        Cache_attribute cacheability, bool io_mem,
 			        unsigned l2size = L4_LOG2_PAGESIZE,
 			        bool rw = true, bool grant = false)
 			:
 				_dst_addr(dst_addr),
 				_fpage(Fiasco::l4_fpage(src_addr, l2size, rw, grant))
 			{
-				if (write_combined)
+				if (cacheability == WRITE_COMBINED)
 					_fpage.fp.cache = Fiasco::L4_FPAGE_BUFFERABLE;
 			}