hw: correct the ARM cache maintainance operations

This commit fixes the following issues regarding cache maintainance
under ARM:

* read out I-, and D-cache line size at runtime and use the correct one
* remove 'update_data_region' call from unprivileged syscalls
* rename 'update_instr_region' syscall to 'cache_coherent_region' to
  reflect what it doing, namely make I-, and D-cache coherent
* restrict 'cache_coherent_region' syscall to one page at a time
* lookup the region given in a 'cache_coherent_region' syscall in the
  page-table of the PD to prevent machine exceptions in the kernel
* only clean D-cache lines, do not invalidate them when pages where
  added on Cortex-A8 and ARMv6 (MMU sees phys. memory here)
* remove unused code relicts of cache maintainance

In addition it introduces per architecture memory clearance functions
used by core, when preparing new dataspaces. Thereby, it optimizes:

* on ARMv7 using per-word assignments
* on ARMv8 using cacheline zeroing
* on x86_64 using 'rept stosq' assembler instruction

Fix #3685

repos/base/include/drivers/defs/exynos5.h

@@ -55,9 +55,6 @@ namespace Exynos5 {
 		MCT_IRQ_L0    = 152,
 		MCT_IRQ_L1    = 153,
 
-		/* CPU cache */
-		CACHE_LINE_SIZE_LOG2 = 6,
-
 		/* IRAM */
 		IRAM_BASE = 0x02020000,
 

repos/base/include/drivers/defs/imx53.h

@@ -106,9 +106,6 @@ namespace Imx53 {
 
 		M4IF_BASE          = 0x63fd8000,
 		M4IF_SIZE          = 0x00001000,
-
-		/* CPU cache */
-		CACHE_LINE_SIZE_LOG2 = 6,
 	};
 };
 

repos/base/include/drivers/defs/imx6.h

@@ -52,9 +52,6 @@ namespace Imx6 {
 		/* System reset controller */
 		SRC_MMIO_BASE = 0x20d8000,
 
-		/* CPU cache */
-		CACHE_LINE_SIZE_LOG2 = 5,
-
 		/* SD host controller */
 		SDHC_1_IRQ       = 54,
 		SDHC_1_MMIO_BASE = 0x02190000,

repos/base/include/drivers/defs/imx7d_sabre.h

@@ -37,8 +37,6 @@ namespace Imx7d_sabre {
 		UART_1_MMIO_SIZE            = 0x10000UL,
 
 		TIMER_CLOCK                 = 1000000000UL,
-
-		CACHE_LINE_SIZE_LOG2        = 6,
 	};
 }
 

repos/base/include/drivers/defs/panda.h

@@ -90,9 +90,6 @@ namespace Panda {
 
 		/* SD card */
 		HSMMC_IRQ = 115,
-
-		/* CPU cache */
-		CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
 	};
 };
 

repos/base/include/drivers/defs/pbxa9.h

@@ -74,9 +74,6 @@ namespace Pbxa9 {
 		/* SD card */
 		PL180_IRQ_0 = 49,
 		PL180_IRQ_1 = 50,
-
-		/* CPU cache */
-		CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
 	};
 };
 

repos/base/include/drivers/defs/rpi.h

@@ -62,9 +62,6 @@ namespace Rpi {
 		/* USB host controller */
 		DWC_IRQ = 17,
 
-		/* CPU cache */
-		CACHE_LINE_SIZE_LOG2 = 5,
-
 		/* SD card */
 		SDHCI_BASE = MMIO_0_BASE + 0x300000,
 		SDHCI_SIZE = 0x100,

repos/base/include/drivers/defs/zynq.h

@@ -52,7 +52,6 @@ namespace Zynq {
 		/* CPU cache */
 		PL310_MMIO_BASE      = MMIO_1_BASE + 0xF02000,
 		PL310_MMIO_SIZE      = 0x1000,
-		CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
 
 		/* TTC (triple timer counter) */
 		TTC0_MMIO_BASE = MMIO_1_BASE + 0x1000,