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Retire Exynos 5 support (fix #3725)

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This commit is contained in:
Stefan Kalkowski
2020-04-07 00:42:50 +02:00
committed by Christian Helmuth
parent 941e918b46
commit 0e49336b96
106 changed files with 15 additions and 7551 deletions
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18
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-arndale.mk
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/arndale
SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/arndale/platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
SRC_S += bootstrap/spec/arm/crt0.s
NR_OF_CPUS = 2
#
# we need more specific compiler hints for some 'special' assembly code
# override -march=armv7-a because it conflicts with -mcpu=cortex-a15
#
CC_MARCH = -mcpu=cortex-a15 -mfpu=vfpv3 -mfloat-abi=softfp
include $(REP_DIR)/lib/mk/bootstrap-hw.inc

10
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-odroid_xu.mk
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@@ -1,10 +0,0 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/odroid_xu
SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/odroid_xu/platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
SRC_S += bootstrap/spec/arm/crt0.s
include $(REP_DIR)/lib/mk/bootstrap-hw.inc

33
repos/base-hw/lib/mk/spec/arm_v7/core-hw-arndale.mk
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@@ -1,33 +0,0 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \date 2015-02-09
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/arndale
INC_DIR += $(REP_DIR)/src/core/spec/arm/virtualization
# add C++ sources
SRC_CC += kernel/vm_thread_on.cc
SRC_CC += spec/arm/gicv2.cc
SRC_CC += spec/arm/virtualization/gicv2.cc
SRC_CC += spec/arm_v7/virtualization/kernel/vm.cc
SRC_CC += spec/arm/virtualization/platform_services.cc
SRC_CC += spec/arm/virtualization/vm_session_component.cc
SRC_CC += vm_session_common.cc
SRC_CC += vm_session_component.cc
# add assembly sources
SRC_S += spec/arm_v7/virtualization/exception_vector.s
NR_OF_CPUS = 2
#
# we need more specific compiler hints for some 'special' assembly code
# override -march=armv7-a because it conflicts with -mcpu=cortex-a15
#
CC_MARCH = -mcpu=cortex-a15 -mfpu=vfpv3 -mfloat-abi=softfp
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/exynos5/core-hw.inc

16
repos/base-hw/lib/mk/spec/arm_v7/core-hw-odroid_xu.mk
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@@ -1,16 +0,0 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \date 2015-02-09
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/odroid_xu
# add C++ sources
SRC_CC += spec/arm/gicv2.cc
SRC_CC += kernel/vm_thread_off.cc
SRC_CC += platform_services.cc
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/exynos5/core-hw.inc

14
repos/base-hw/lib/mk/spec/exynos5/core-hw.inc
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@@ -1,14 +0,0 @@
#
# \brief Build config for Genodes core process
# \author Martin Stein
# \date 2011-12-16
#
# add include paths
INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/exynos5
# add C++ sources
SRC_CC += spec/arm/exynos_mct.cc
# include less specific configuration
include $(BASE_DIR)/../base-hw/lib/mk/spec/cortex_a15/core-hw.inc

7
repos/base-hw/recipes/src/base-hw-arndale/content.mk
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@@ -1,7 +0,0 @@
BOARD = arndale
include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc
content: enable_board_spec
enable_board_spec: etc/specs.conf
echo "SPECS += arndale" >> etc/specs.conf

1
repos/base-hw/recipes/src/base-hw-arndale/hash
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@@ -1 +0,0 @@
2020-04-16 1e7c44e2b6b3a2a9a687a734f8d7a8772eba1944

2
repos/base-hw/recipes/src/base-hw-arndale/used_apis
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base-hw
base

7
repos/base-hw/recipes/src/base-hw-odroid_xu/content.mk
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BOARD = odroid_xu
include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc
content: enable_board_spec
enable_board_spec: etc/specs.conf
echo "SPECS += odroid_xu" >> etc/specs.conf

1
repos/base-hw/recipes/src/base-hw-odroid_xu/hash
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@@ -1 +0,0 @@
2020-04-16 bc10b21e3f2785dec9a7b7a19340a031a834eaee

2
repos/base-hw/recipes/src/base-hw-odroid_xu/used_apis
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base-hw
base

28
repos/base-hw/src/bootstrap/spec/arndale/board.h
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/*
* \brief Arndale specific board definitions
* \author Stefan Kalkowski
* \date 2017-04-03
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
#include <hw/spec/arm/arndale_board.h>
#include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h>
#include <hw/spec/arm/gicv2.h>
namespace Board {
using namespace Hw::Arndale_board;
using Pic = Hw::Gicv2;
static constexpr bool NON_SECURE = true;
}
#endif /* _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_ */

25
repos/base-hw/src/bootstrap/spec/arndale/cpu.cc
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@@ -1,25 +0,0 @@
/*
* \brief CPU-specific initialization code for Arndale
* \author Stefan Kalkowski
* \date 2016-01-07
*/
/*
* Copyright (C) 2016-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* core includes */
#include <cpu.h>
#include <translation_table.h>
void Genode::Cpu::init(Genode::Translation_table & table)
{
prepare_nonsecure_world();
prepare_hypervisor(table);
switch_to_supervisor_mode();
}

84
repos/base-hw/src/bootstrap/spec/arndale/platform.cc
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@@ -1,84 +0,0 @@
/*
* \brief Parts of platform that are specific to Arndale
* \author Martin Stein
* \date 2012-04-27
*/
/*
* Copyright (C) 2012-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <spec/arm/cortex_a7_a15_virtualization.h>
#include <platform.h>
extern "C" void * _start_setup_stack; /* entrypoint for non-boot CPUs */
static unsigned char hyp_mode_stack[1024]; /* hypervisor mode's kernel stack */
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
Memory_region { MCT_MMIO_BASE, MCT_MMIO_SIZE },
Memory_region { UART_2_MMIO_BASE, UART_2_MMIO_SIZE }) { }
static inline void switch_to_supervisor_mode()
{
using Cpsr = Hw::Arm_cpu::Psr;
Cpsr::access_t cpsr = 0;
Cpsr::M::set(cpsr, Cpsr::M::SVC);
Cpsr::F::set(cpsr, 1);
Cpsr::I::set(cpsr, 1);
asm volatile (
"msr sp_svc, sp \n" /* copy current mode's sp */
"msr lr_svc, lr \n" /* copy current mode's lr */
"msr elr_hyp, lr \n" /* copy current mode's lr to hyp lr */
"msr sp_hyp, %[stack] \n" /* copy to hyp stack pointer */
"msr spsr_cxfs, %[cpsr] \n" /* set psr for supervisor mode */
"adr lr, 1f \n" /* load exception return address */
"eret \n" /* exception return */
"1:":: [cpsr] "r" (cpsr), [stack] "r" (&hyp_mode_stack));
}
unsigned Bootstrap::Platform::enable_mmu()
{
static volatile bool primary_cpu = true;
static unsigned long timer_freq = 24000000;
/* locally initialize interrupt controller */
::Board::Pic pic { };
volatile unsigned long * mct_control = (unsigned long*) 0x101C0240;
*mct_control = 0x100;
prepare_nonsecure_world(timer_freq);
prepare_hypervisor((addr_t)core_pd->table_base);
switch_to_supervisor_mode();
Cpu::Sctlr::init();
Cpu::Cpsr::init();
/* primary cpu wakes up all others */
if (primary_cpu && NR_OF_CPUS > 1) {
Cpu::invalidate_data_cache();
primary_cpu = false;
Cpu::wake_up_all_cpus(&_start_setup_stack);
}
Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
}
void Board::Cpu::wake_up_all_cpus(void * const ip)
{
*(void * volatile *)Board::IRAM_BASE = ip;
asm volatile("dsb; sev;");
}

28
repos/base-hw/src/bootstrap/spec/odroid_xu/board.h
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@@ -1,28 +0,0 @@
/*
* \brief Odroid XU specific board definitions
* \author Stefan Kalkowski
* \date 2017-04-03
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
#include <hw/spec/arm/odroid_xu_board.h>
#include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h>
#include <hw/spec/arm/gicv2.h>
namespace Board {
using namespace Hw::Odroid_xu_board;
using Pic = Hw::Gicv2;
static constexpr bool NON_SECURE = false;
}
#endif /* _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_ */

36
repos/base-hw/src/bootstrap/spec/odroid_xu/platform.cc
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@@ -1,36 +0,0 @@
/*
* \brief Parts of platform that are specific to Odroid XU
* \author Martin Stein
* \date 2012-04-27
*/
/*
* Copyright (C) 2012-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <platform.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
Memory_region { IRQ_CONTROLLER_VT_CTRL_BASE, IRQ_CONTROLLER_VT_CTRL_SIZE },
Memory_region { MCT_MMIO_BASE, MCT_MMIO_SIZE },
Memory_region { UART_2_MMIO_BASE, UART_2_MMIO_SIZE }) { }
unsigned Bootstrap::Platform::enable_mmu()
{
/* locally initialize interrupt controller */
::Board::Pic pic { };
Cpu::Sctlr::init();
Cpu::Cpsr::init();
Cpu::invalidate_data_cache();
Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
return 0;
}

97
repos/base-hw/src/core/spec/arm/exynos_mct.cc
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@@ -1,97 +0,0 @@
/*
* \brief Timer driver for core
* \author Stefan Kalkowski
* \author Martin stein
* \date 2013-01-10
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* core include */
#include <kernel/timer.h>
#include <board.h>
#include <platform.h>
#include <drivers/timer/util.h>
using namespace Genode;
using namespace Kernel;
unsigned Timer::interrupt_id() const
{
switch (_device.cpu_id) {
case 0: return Board::MCT_IRQ_L0;
case 1: return Board::MCT_IRQ_L1;
default: return 0;
}
}
Board::Timer::Timer(unsigned cpu_id)
:
Mmio(Platform::mmio_to_virt(Board::MCT_MMIO_BASE)),
local(Platform::mmio_to_virt(Board::MCT_MMIO_BASE)
+ (cpu_id ? L1 : L0)),
ticks_per_ms(calc_ticks_per_ms(Board::MCT_CLOCK)),
cpu_id(cpu_id)
{
static unsigned initialized = 0;
if (initialized++) return;
Mct_cfg::access_t mct_cfg = 0;
Mct_cfg::Prescaler::set(mct_cfg, PRESCALER);
Mct_cfg::Div_mux::set(mct_cfg, DIV_MUX);
write<Mct_cfg>(mct_cfg);
}
Board::Timer::Local::Local(Genode::addr_t base)
: Mmio(base)
{
write<Int_enb>(Int_enb::Frceie::bits(1));
acked_write<Tcntb, Wstat::Tcntb>(0xffffffff);
acked_write<Frcntb, Wstat::Frcntb>(0xffffffff);
Tcon::access_t tcon = 0;
Tcon::Frc_start::set(tcon, 1);
Tcon::Timer_start::set(tcon, 1);
acked_write<Tcon, Wstat::Tcon>(tcon);
}
void Timer::_start_one_shot(time_t const ticks)
{
using Device = Board::Timer;
_device.local.cnt = _device.local.read<Device::Local::Tcnto>();
_device.local.write<Device::Local::Int_cstat::Frccnt>(1);
_device.local.acked_write<Device::Local::Frcntb,
Device::Local::Wstat::Frcntb>(ticks);
}
time_t Timer::_duration() const
{
using Tcnto = Board::Timer::Local::Tcnto;
unsigned long ret = _device.local.cnt - _device.local.read<Tcnto>();
return ret;
}
time_t Timer::ticks_to_us(time_t const ticks) const {
return timer_ticks_to_us(ticks, _device.ticks_per_ms); }
time_t Timer::us_to_ticks(time_t const us) const {
return (us / 1000) * _device.ticks_per_ms; }
time_t Timer::_max_value() const {
return 0xffffffff; }

121
repos/base-hw/src/core/spec/arm/exynos_mct.h
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@@ -1,121 +0,0 @@
/*
* \brief Timer driver for core
* \author Martin stein
* \date 2013-01-10
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Kernel OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__CORE__SPEC__ARM__EXYNOS_MCT_H_
#define _SRC__CORE__SPEC__ARM__EXYNOS_MCT_H_
/* Kernel includes */
#include <util/mmio.h>
/* base-hw includes */
#include <kernel/types.h>
namespace Board { class Timer; }
struct Board::Timer : Genode::Mmio
{
enum {
PRESCALER = 1,
DIV_MUX = 0,
};
/**
* MCT configuration
*/
struct Mct_cfg : Register<0x0, 32>
{
struct Prescaler : Bitfield<0, 8> { };
struct Div_mux : Bitfield<8, 3> { };
};
/*****************
** Local timer **
*****************/
enum Local_timer_offset { L0 = 0x300, L1 = 0x400 };
struct Local : Genode::Mmio {
struct Tcntb : Register<0x0, 32> { };
struct Tcnto : Register<0x4, 32> { };
struct Icntb : Register<0x8, 32> { };
struct Icnto : Register<0xc, 32> { };
struct Frcntb : Register<0x10, 32> { };
struct Frcnto : Register<0x14, 32> { };
struct Tcon : Register<0x20, 32>
{
struct Timer_start : Bitfield<0, 1> { };
struct Irq_start : Bitfield<1, 1> { };
struct Irq_type : Bitfield<2, 1> { };
struct Frc_start : Bitfield<3, 1> { };
};
struct Int_cstat : Register<0x30, 32, true>
{
struct Intcnt : Bitfield<0, 1> { };
struct Frccnt : Bitfield<1, 1> { };
};
struct Int_enb : Register<0x34, 32>
{
struct Inteie : Bitfield<0, 1> { };
struct Frceie : Bitfield<1, 1> { };
};
struct Wstat : Register<0x40, 32, true>
{
struct Tcntb : Bitfield<0, 1> { };
struct Icntb : Bitfield<1, 1> { };
struct Frcntb : Bitfield<2, 1> { };
struct Tcon : Bitfield<3, 1> { };
};
Tcnto::access_t cnt = { 0 };
/**
* Write to reg that replies via ack bit and clear ack bit
*/
template <typename DEST, typename ACK>
void acked_write(typename DEST::Register_base::access_t const v)
{
typedef typename DEST::Register_base Dest;
typedef typename ACK::Bitfield_base Ack;
write<Dest>(v);
while (!read<Ack>());
write<Ack>(1);
}
void update_cnt() { cnt = read<Tcnto>(); }
Local(Genode::addr_t base);
};
/**
* Calculate amount of ticks per ms for specific input clock
*
* \param clock input clock
*/
Kernel::time_t static calc_ticks_per_ms(unsigned const clock) {
return clock / (PRESCALER + 1) / (1 << DIV_MUX) / 1000; }
Local local;
unsigned const ticks_per_ms;
unsigned const cpu_id;
Timer(unsigned cpu_id);
};
#endif /* _SRC__CORE__SPEC__ARM__EXYNOS_MCT_H_ */

2
repos/base-hw/src/core/spec/arm/virtualization/platform_services.cc
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@@ -1,5 +1,5 @@
/*
* \brief Platform specific services for Arndale
* \brief Platform specific services for ARM with virtualization
* \author Stefan Kalkowski
* \date 2014-07-08
*/

33
repos/base-hw/src/core/spec/arndale/board.h
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@@ -1,33 +0,0 @@
/*
* \brief Board driver for core
* \author Stefan Kalkowski
* \date 2017-04-27
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__ARNDALE__BOARD_H_
#define _CORE__SPEC__ARNDALE__BOARD_H_
#include <spec/arm/virtualization/gicv2.h>
#include <hw/spec/arm/arndale_board.h>
#include <spec/arm/exynos_mct.h>
#include <spec/arm/cpu/vm_state_virtualization.h>
#include <spec/arm/virtualization/board.h>
namespace Kernel { class Cpu; }
namespace Board {
using namespace Hw::Arndale_board;
struct Virtual_local_pic {};
enum { VCPU_MAX = 1 };
}
#endif /* _CORE__SPEC__ARNDALE__BOARD_H_ */

27
repos/base-hw/src/core/spec/odroid_xu/board.h
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@@ -1,27 +0,0 @@
/*
* \brief Board driver for core
* \author Stefan Kalkowski
* \date 2017-04-27
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__ODROID_XU__BOARD_H_
#define _CORE__SPEC__ODROID_XU__BOARD_H_
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/odroid_xu_board.h>
#include <spec/arm/exynos_mct.h>
namespace Board {
using namespace Hw::Odroid_xu_board;
using Pic = Hw::Gicv2;
}
#endif /* _CORE__SPEC__ODROID_XU__BOARD_H_ */

34
repos/base-hw/src/include/hw/spec/arm/arndale_board.h
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@@ -1,34 +0,0 @@
/*
* \brief Arndale specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-15
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_
#include <drivers/defs/arndale.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/boot_info.h>
#include <hw/spec/arm/cortex_a15.h>
namespace Hw::Arndale_board {
using namespace Arndale;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_ */

33
repos/base-hw/src/include/hw/spec/arm/odroid_xu_board.h
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@@ -1,33 +0,0 @@
/*
* \brief Odroid XU specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_
#include <drivers/defs/odroid_xu.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/boot_info.h>
#include <hw/spec/arm/cortex_a15.h>
namespace Hw::Odroid_xu_board {
using namespace Odroid_xu;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_ */