diff --git a/lib/mk/spec/zynq_parallella/bootstrap-hw.mk b/lib/mk/spec/zynq_parallella/bootstrap-hw.mk
index 21312e6..6958948 100644
--- a/lib/mk/spec/zynq_parallella/bootstrap-hw.mk
+++ b/lib/mk/spec/zynq_parallella/bootstrap-hw.mk
@@ -1,14 +1,19 @@
 TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
 BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
 
-INC_DIR += $(BASE_HW_DIR)/src/bootstrap/spec/zynq
+INC_DIR += $(REP_DIR)/src/bootstrap/spec/zynq_parallella
 
 SRC_S   += bootstrap/spec/arm/crt0.s
 
 SRC_CC  += bootstrap/spec/arm/cpu.cc
 SRC_CC  += bootstrap/spec/arm/cortex_a9_mmu.cc
 SRC_CC  += bootstrap/spec/arm/pic.cc
-SRC_CC  += bootstrap/spec/zynq/platform.cc
+SRC_CC  += bootstrap/spec/zynq_parallella/platform.cc
 SRC_CC  += hw/spec/arm/arm_v7_cpu.cc
+SRC_CC  += hw/spec/32bit/memory_map.cc
+
+NR_OF_CPUS = 1
+
+vpath bootstrap/spec/zynq_parallella/platform.cc $(REP_DIR)/src/
 
 include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc
diff --git a/lib/mk/spec/zynq_parallella/core-hw.mk b/lib/mk/spec/zynq_parallella/core-hw.mk
index 22b11da..f1886aa 100644
--- a/lib/mk/spec/zynq_parallella/core-hw.mk
+++ b/lib/mk/spec/zynq_parallella/core-hw.mk
@@ -10,5 +10,7 @@ BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
 # add include paths
 INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_parallella
 
+NR_OF_CPUS = 1
+
 # include less specific configuration
 include $(BASE_HW_DIR)/lib/mk/spec/zynq/core-hw.inc
diff --git a/lib/mk/spec/zynq_zc702/bootstrap-hw.mk b/lib/mk/spec/zynq_zc702/bootstrap-hw.mk
index 21312e6..7fc75d5 100644
--- a/lib/mk/spec/zynq_zc702/bootstrap-hw.mk
+++ b/lib/mk/spec/zynq_zc702/bootstrap-hw.mk
@@ -1,14 +1,19 @@
 TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
 BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
 
-INC_DIR += $(BASE_HW_DIR)/src/bootstrap/spec/zynq
+INC_DIR += $(REP_DIR)/src/bootstrap/spec/zynq_zc702
 
 SRC_S   += bootstrap/spec/arm/crt0.s
 
 SRC_CC  += bootstrap/spec/arm/cpu.cc
 SRC_CC  += bootstrap/spec/arm/cortex_a9_mmu.cc
 SRC_CC  += bootstrap/spec/arm/pic.cc
-SRC_CC  += bootstrap/spec/zynq/platform.cc
+SRC_CC  += bootstrap/spec/zynq_zc702/platform.cc
 SRC_CC  += hw/spec/arm/arm_v7_cpu.cc
+SRC_CC  += hw/spec/32bit/memory_map.cc
+
+NR_OF_CPUS = 1
+
+vpath bootstrap/spec/zynq_zc702/platform.cc $(REP_DIR)/src/
 
 include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc
diff --git a/lib/mk/spec/zynq_zc702/core-hw.mk b/lib/mk/spec/zynq_zc702/core-hw.mk
index 1d53411..00a403c 100644
--- a/lib/mk/spec/zynq_zc702/core-hw.mk
+++ b/lib/mk/spec/zynq_zc702/core-hw.mk
@@ -10,5 +10,7 @@ BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
 # add include paths
 INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc702
 
+NR_OF_CPUS = 1
+
 # include less specific configuration
 include $(BASE_HW_DIR)/lib/mk/spec/zynq/core-hw.inc
diff --git a/lib/mk/spec/zynq_zc706/bootstrap-hw.mk b/lib/mk/spec/zynq_zc706/bootstrap-hw.mk
index 21312e6..392e8db 100644
--- a/lib/mk/spec/zynq_zc706/bootstrap-hw.mk
+++ b/lib/mk/spec/zynq_zc706/bootstrap-hw.mk
@@ -1,14 +1,19 @@
 TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
 BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
 
-INC_DIR += $(BASE_HW_DIR)/src/bootstrap/spec/zynq
+INC_DIR += $(REP_DIR)/src/bootstrap/spec/zynq_zc706
 
 SRC_S   += bootstrap/spec/arm/crt0.s
 
 SRC_CC  += bootstrap/spec/arm/cpu.cc
 SRC_CC  += bootstrap/spec/arm/cortex_a9_mmu.cc
 SRC_CC  += bootstrap/spec/arm/pic.cc
-SRC_CC  += bootstrap/spec/zynq/platform.cc
+SRC_CC  += bootstrap/spec/zynq_zc706/platform.cc
 SRC_CC  += hw/spec/arm/arm_v7_cpu.cc
+SRC_CC  += hw/spec/32bit/memory_map.cc
+
+NR_OF_CPUS = 1
+
+vpath bootstrap/spec/zynq_zc706/platform.cc $(REP_DIR)/src/
 
 include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc
diff --git a/lib/mk/spec/zynq_zc706/core-hw.mk b/lib/mk/spec/zynq_zc706/core-hw.mk
index ea2f27e..fd4e1e3 100644
--- a/lib/mk/spec/zynq_zc706/core-hw.mk
+++ b/lib/mk/spec/zynq_zc706/core-hw.mk
@@ -10,5 +10,7 @@ BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
 # add include paths
 INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc706
 
+NR_OF_CPUS = 1
+
 # include less specific configuration
 include $(BASE_HW_DIR)/lib/mk/spec/zynq/core-hw.inc
diff --git a/lib/mk/spec/zynq_zedboard/bootstrap-hw.mk b/lib/mk/spec/zynq_zedboard/bootstrap-hw.mk
index 21312e6..2f6b57a 100644
--- a/lib/mk/spec/zynq_zedboard/bootstrap-hw.mk
+++ b/lib/mk/spec/zynq_zedboard/bootstrap-hw.mk
@@ -1,14 +1,19 @@
 TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
 BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
 
-INC_DIR += $(BASE_HW_DIR)/src/bootstrap/spec/zynq
+INC_DIR += $(REP_DIR)/src/bootstrap/spec/zynq_zedboard
 
 SRC_S   += bootstrap/spec/arm/crt0.s
 
 SRC_CC  += bootstrap/spec/arm/cpu.cc
 SRC_CC  += bootstrap/spec/arm/cortex_a9_mmu.cc
 SRC_CC  += bootstrap/spec/arm/pic.cc
-SRC_CC  += bootstrap/spec/zynq/platform.cc
+SRC_CC  += bootstrap/spec/zynq_zedboard/platform.cc
 SRC_CC  += hw/spec/arm/arm_v7_cpu.cc
+SRC_CC  += hw/spec/32bit/memory_map.cc
+
+NR_OF_CPUS = 1
+
+vpath bootstrap/spec/zynq_zedboard/platform.cc $(REP_DIR)/src/
 
 include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc
diff --git a/lib/mk/spec/zynq_zedboard/core-hw.mk b/lib/mk/spec/zynq_zedboard/core-hw.mk
index 3a28d29..cfb7be5 100644
--- a/lib/mk/spec/zynq_zedboard/core-hw.mk
+++ b/lib/mk/spec/zynq_zedboard/core-hw.mk
@@ -10,5 +10,7 @@ BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
 # add include paths
 INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zedboard
 
+NR_OF_CPUS = 1
+
 # include less specific configuration
 include $(BASE_HW_DIR)/lib/mk/spec/zynq/core-hw.inc
diff --git a/src/bootstrap/spec/zynq_parallella/board.h b/src/bootstrap/spec/zynq_parallella/board.h
new file mode 100644
index 0000000..479f7ea
--- /dev/null
+++ b/src/bootstrap/spec/zynq_parallella/board.h
@@ -0,0 +1,38 @@
+/*
+ * \brief   Zynq specific board definitions
+ * \author  Stefan Kalkowski
+ * \date    2017-02-20
+ */
+
+/*
+ * Copyright (C) 2017 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU Affero General Public License version 3.
+ */
+
+#ifndef _SRC__BOOTSTRAP__SPEC__ZYNQ_PARALLELLA__BOARD_H_
+#define _SRC__BOOTSTRAP__SPEC__ZYNQ_PARALLELLA__BOARD_H_
+
+#include <drivers/defs/zynq_parallella.h>
+#include <drivers/uart/xilinx.h>
+#include <hw/spec/arm/cortex_a9.h>
+#include <hw/spec/arm/pl310.h>
+
+#include <spec/arm/cortex_a9_actlr.h>
+#include <spec/arm/cortex_a9_page_table.h>
+#include <spec/arm/cpu.h>
+#include <spec/arm/pic.h>
+
+namespace Board {
+	using namespace Zynq_parallella;
+	using L2_cache = Hw::Pl310;
+	using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
+	using Serial   = Genode::Xilinx_uart;
+
+	enum {
+		UART_BASE  = UART_1_MMIO_BASE,
+	};
+}
+
+#endif /* _SRC__BOOTSTRAP__SPEC__ZYNQ_PARALLELLA__BOARD_H_ */
diff --git a/src/bootstrap/spec/zynq_parallella/platform.cc b/src/bootstrap/spec/zynq_parallella/platform.cc
new file mode 100644
index 0000000..4602b30
--- /dev/null
+++ b/src/bootstrap/spec/zynq_parallella/platform.cc
@@ -0,0 +1,33 @@
+/*
+ * \brief   Platform implementations specific for base-hw and Zynq
+ * \author  Johannes Schlatow
+ * \author  Stefan Kalkowski
+ * \date    2014-12-15
+ */
+
+/*
+ * Copyright (C) 2014-2017 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU Affero General Public License version 3.
+ */
+
+/* core includes */
+#include <platform.h>
+
+using namespace Board;
+
+Bootstrap::Platform::Board::Board()
+: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
+                                    RAM_0_SIZE - 0x1000 }),
+  late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
+  core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
+                            CORTEX_A9_PRIVATE_MEM_SIZE },
+            Memory_region { UART_1_MMIO_BASE,
+                            UART_SIZE },
+            Memory_region { PL310_MMIO_BASE,
+                            PL310_MMIO_SIZE }) { }
+
+
+bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
+	return false; }
diff --git a/src/bootstrap/spec/zynq_zc702/board.h b/src/bootstrap/spec/zynq_zc702/board.h
new file mode 100644
index 0000000..4bd2bba
--- /dev/null
+++ b/src/bootstrap/spec/zynq_zc702/board.h
@@ -0,0 +1,38 @@
+/*
+ * \brief   Zynq specific board definitions
+ * \author  Stefan Kalkowski
+ * \date    2017-02-20
+ */
+
+/*
+ * Copyright (C) 2017 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU Affero General Public License version 3.
+ */
+
+#ifndef _SRC__BOOTSTRAP__SPEC__ZYNQ_ZC702__BOARD_H_
+#define _SRC__BOOTSTRAP__SPEC__ZYNQ_ZC702__BOARD_H_
+
+#include <drivers/defs/zynq_zc702.h>
+#include <drivers/uart/xilinx.h>
+#include <hw/spec/arm/cortex_a9.h>
+#include <hw/spec/arm/pl310.h>
+
+#include <spec/arm/cortex_a9_actlr.h>
+#include <spec/arm/cortex_a9_page_table.h>
+#include <spec/arm/cpu.h>
+#include <spec/arm/pic.h>
+
+namespace Board {
+	using namespace Zynq_zc702;
+	using L2_cache = Hw::Pl310;
+	using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
+	using Serial   = Genode::Xilinx_uart;
+
+	enum {
+		UART_BASE  = UART_1_MMIO_BASE,
+	};
+}
+
+#endif /* _SRC__BOOTSTRAP__SPEC__ZYNQ_ZC702__BOARD_H_ */
diff --git a/src/bootstrap/spec/zynq_zc702/platform.cc b/src/bootstrap/spec/zynq_zc702/platform.cc
new file mode 100644
index 0000000..4602b30
--- /dev/null
+++ b/src/bootstrap/spec/zynq_zc702/platform.cc
@@ -0,0 +1,33 @@
+/*
+ * \brief   Platform implementations specific for base-hw and Zynq
+ * \author  Johannes Schlatow
+ * \author  Stefan Kalkowski
+ * \date    2014-12-15
+ */
+
+/*
+ * Copyright (C) 2014-2017 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU Affero General Public License version 3.
+ */
+
+/* core includes */
+#include <platform.h>
+
+using namespace Board;
+
+Bootstrap::Platform::Board::Board()
+: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
+                                    RAM_0_SIZE - 0x1000 }),
+  late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
+  core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
+                            CORTEX_A9_PRIVATE_MEM_SIZE },
+            Memory_region { UART_1_MMIO_BASE,
+                            UART_SIZE },
+            Memory_region { PL310_MMIO_BASE,
+                            PL310_MMIO_SIZE }) { }
+
+
+bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
+	return false; }
diff --git a/src/bootstrap/spec/zynq_zc706/board.h b/src/bootstrap/spec/zynq_zc706/board.h
new file mode 100644
index 0000000..28746a7
--- /dev/null
+++ b/src/bootstrap/spec/zynq_zc706/board.h
@@ -0,0 +1,38 @@
+/*
+ * \brief   Zynq specific board definitions
+ * \author  Stefan Kalkowski
+ * \date    2017-02-20
+ */
+
+/*
+ * Copyright (C) 2017 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU Affero General Public License version 3.
+ */
+
+#ifndef _SRC__BOOTSTRAP__SPEC__ZYNQ_ZC706__BOARD_H_
+#define _SRC__BOOTSTRAP__SPEC__ZYNQ_ZC706__BOARD_H_
+
+#include <drivers/defs/zynq_zc706.h>
+#include <drivers/uart/xilinx.h>
+#include <hw/spec/arm/cortex_a9.h>
+#include <hw/spec/arm/pl310.h>
+
+#include <spec/arm/cortex_a9_actlr.h>
+#include <spec/arm/cortex_a9_page_table.h>
+#include <spec/arm/cpu.h>
+#include <spec/arm/pic.h>
+
+namespace Board {
+	using namespace Zynq_zc706;
+	using L2_cache = Hw::Pl310;
+	using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
+	using Serial   = Genode::Xilinx_uart;
+
+	enum {
+		UART_BASE  = UART_1_MMIO_BASE,
+	};
+}
+
+#endif /* _SRC__BOOTSTRAP__SPEC__ZYNQ_ZC706__BOARD_H_ */
diff --git a/src/bootstrap/spec/zynq_zc706/platform.cc b/src/bootstrap/spec/zynq_zc706/platform.cc
new file mode 100644
index 0000000..4602b30
--- /dev/null
+++ b/src/bootstrap/spec/zynq_zc706/platform.cc
@@ -0,0 +1,33 @@
+/*
+ * \brief   Platform implementations specific for base-hw and Zynq
+ * \author  Johannes Schlatow
+ * \author  Stefan Kalkowski
+ * \date    2014-12-15
+ */
+
+/*
+ * Copyright (C) 2014-2017 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU Affero General Public License version 3.
+ */
+
+/* core includes */
+#include <platform.h>
+
+using namespace Board;
+
+Bootstrap::Platform::Board::Board()
+: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
+                                    RAM_0_SIZE - 0x1000 }),
+  late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
+  core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
+                            CORTEX_A9_PRIVATE_MEM_SIZE },
+            Memory_region { UART_1_MMIO_BASE,
+                            UART_SIZE },
+            Memory_region { PL310_MMIO_BASE,
+                            PL310_MMIO_SIZE }) { }
+
+
+bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
+	return false; }
diff --git a/src/bootstrap/spec/zynq_zedboard/board.h b/src/bootstrap/spec/zynq_zedboard/board.h
new file mode 100644
index 0000000..73ee418
--- /dev/null
+++ b/src/bootstrap/spec/zynq_zedboard/board.h
@@ -0,0 +1,38 @@
+/*
+ * \brief   Zynq specific board definitions
+ * \author  Stefan Kalkowski
+ * \date    2017-02-20
+ */
+
+/*
+ * Copyright (C) 2017 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU Affero General Public License version 3.
+ */
+
+#ifndef _SRC__BOOTSTRAP__SPEC__ZYNQ_ZEDBOARD__BOARD_H_
+#define _SRC__BOOTSTRAP__SPEC__ZYNQ_ZEDBOARD__BOARD_H_
+
+#include <drivers/defs/zynq_zedboard.h>
+#include <drivers/uart/xilinx.h>
+#include <hw/spec/arm/cortex_a9.h>
+#include <hw/spec/arm/pl310.h>
+
+#include <spec/arm/cortex_a9_actlr.h>
+#include <spec/arm/cortex_a9_page_table.h>
+#include <spec/arm/cpu.h>
+#include <spec/arm/pic.h>
+
+namespace Board {
+	using namespace Zynq_zedboard;
+	using L2_cache = Hw::Pl310;
+	using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
+	using Serial   = Genode::Xilinx_uart;
+
+	enum {
+		UART_BASE  = UART_1_MMIO_BASE,
+	};
+}
+
+#endif /* _SRC__BOOTSTRAP__SPEC__ZYNQ_ZEDBOARD__BOARD_H_ */
diff --git a/src/bootstrap/spec/zynq_zedboard/platform.cc b/src/bootstrap/spec/zynq_zedboard/platform.cc
new file mode 100644
index 0000000..4602b30
--- /dev/null
+++ b/src/bootstrap/spec/zynq_zedboard/platform.cc
@@ -0,0 +1,33 @@
+/*
+ * \brief   Platform implementations specific for base-hw and Zynq
+ * \author  Johannes Schlatow
+ * \author  Stefan Kalkowski
+ * \date    2014-12-15
+ */
+
+/*
+ * Copyright (C) 2014-2017 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU Affero General Public License version 3.
+ */
+
+/* core includes */
+#include <platform.h>
+
+using namespace Board;
+
+Bootstrap::Platform::Board::Board()
+: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
+                                    RAM_0_SIZE - 0x1000 }),
+  late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
+  core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
+                            CORTEX_A9_PRIVATE_MEM_SIZE },
+            Memory_region { UART_1_MMIO_BASE,
+                            UART_SIZE },
+            Memory_region { PL310_MMIO_BASE,
+                            PL310_MMIO_SIZE }) { }
+
+
+bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
+	return false; }