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zynq: fix private timer clk in board defs

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Fixes #107
This commit is contained in:
Johannes Schlatow
2018-03-23 13:58:12 +01:00
committed by Norman Feske
parent fb4833f972
commit a564b342c4
4 changed files with 8 additions and 5 deletions
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3
include/drivers/defs/zynq_parallella.h
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@@ -24,10 +24,11 @@ namespace Zynq_parallella {
/* clocks (assuming 6:2:1 mode) */
PS_CLOCK = 33333333,
CPU_1X_CLOCK = 111111100,
CPU_3X2X_CLOCK = 3*CPU_1X_CLOCK,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CPU_3X2X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
SDHCI_BASE = MMIO_0_BASE + 0x101000,

3
include/drivers/defs/zynq_zc702.h
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@@ -23,10 +23,11 @@ namespace Zynq_zc702 {
enum {
/* clocks (assuming 6:2:1 mode) */
CPU_1X_CLOCK = 111111100,
CPU_3X2X_CLOCK = 3*CPU_1X_CLOCK,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CPU_3X2X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
SDHCI_BASE = MMIO_0_BASE + 0x100000,

3
include/drivers/defs/zynq_zc706.h
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@@ -23,10 +23,11 @@ namespace Zynq_zc706 {
enum {
/* clocks (assuming 6:2:1 mode) */
CPU_1X_CLOCK = 111111100,
CPU_3X2X_CLOCK = 3*CPU_1X_CLOCK,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CPU_3X2X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
SDHCI_BASE = MMIO_0_BASE + 0x100000,

4
include/drivers/defs/zynq_zedboard.h
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@@ -33,8 +33,8 @@ namespace Zynq_zedboard {
UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CPU_3X2X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
RAM_0_SIZE = 0x20000000, /* 512MB */