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zynq: update to 17.05

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Ref #74
This commit is contained in:
Johannes Schlatow
2017-08-07 17:29:33 +02:00
committed by Norman Feske
parent 834f98137f
commit 98820ffab4
21 changed files with 153 additions and 169 deletions
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18
include/spec/parallella/drivers/board_base.h → include/drivers/defs/zynq_parallella.h
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@@ -5,26 +5,22 @@
*/ */
/* /*
* Copyright (C) 2015 Genode Labs GmbH * Copyright (C) 2015-2017 Genode Labs GmbH
* *
* This file is part of the Genode OS framework, which is distributed * This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_ #ifndef _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_ #define _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_
#include <spec/zynq/drivers/board_base_support.h> #include <drivers/defs/zynq.h>
namespace Genode { struct Board_base; } namespace Zynq_parallella {
/** using namespace Zynq;
* Base driver for the Parallella platform
*/ enum {
struct Genode::Board_base : Zynq::Board_base
{
enum
{
/* clocks (assuming 6:2:1 mode) */ /* clocks (assuming 6:2:1 mode) */
PS_CLOCK = 33333333, PS_CLOCK = 33333333,
CPU_1X_CLOCK = 111111100, CPU_1X_CLOCK = 111111100,

18
include/spec/zc702/drivers/board_base.h → include/drivers/defs/zynq_zc702.h
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@@ -5,26 +5,22 @@
*/ */
/* /*
* Copyright (C) 2016 Genode Labs GmbH * Copyright (C) 2016-2017 Genode Labs GmbH
* *
* This file is part of the Genode OS framework, which is distributed * This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_ #ifndef _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_ #define _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_
#include <spec/zynq/drivers/board_base_support.h> #include <drivers/defs/zynq.h>
namespace Genode { struct Board_base; } namespace Zynq_zc702 {
/** using namespace Zynq;
* Base driver for the ZC702 platform
*/ enum {
struct Genode::Board_base : Zynq::Board_base
{
enum
{
/* clocks (assuming 6:2:1 mode) */ /* clocks (assuming 6:2:1 mode) */
CPU_1X_CLOCK = 111111100, CPU_1X_CLOCK = 111111100,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK, CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,

18
include/spec/zc706/drivers/board_base.h → include/drivers/defs/zynq_zc706.h
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@@ -5,26 +5,22 @@
*/ */
/* /*
* Copyright (C) 2016 Genode Labs GmbH * Copyright (C) 2016-2017 Genode Labs GmbH
* *
* This file is part of the Genode OS framework, which is distributed * This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_ #ifndef _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_ #define _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_
#include <spec/zynq/drivers/board_base_support.h> #include <drivers/defs/zynq.h>
namespace Genode { struct Board_base; } namespace Zynq_zc706 {
/** using namespace Zynq;
* Base driver for the ZC706 platform
*/ enum {
struct Genode::Board_base : Zynq::Board_base
{
enum
{
/* clocks (assuming 6:2:1 mode) */ /* clocks (assuming 6:2:1 mode) */
CPU_1X_CLOCK = 111111100, CPU_1X_CLOCK = 111111100,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK, CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,

19
include/spec/zedboard/drivers/board_base.h → include/drivers/defs/zynq_zedboard.h
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@@ -5,26 +5,23 @@
*/ */
/* /*
* Copyright (C) 2015 Genode Labs GmbH * Copyright (C) 2015-2017 Genode Labs GmbH
* *
* This file is part of the Genode OS framework, which is distributed * This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_ #ifndef _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_ #define _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_
#include <spec/zynq/drivers/board_base_support.h> #include <drivers/defs/zynq.h>
namespace Genode { struct Board_base; } namespace Zynq_zedboard {
/** using namespace Zynq;
* Base driver for the Zedboard platform
*/ enum {
struct Genode::Board_base : Zynq::Board_base /* clocks (assuming 6:2:1 mode) */
{
enum
{
PS_CLOCK = 33333333, PS_CLOCK = 33333333,
ARM_PLL_CLOCK = 1333333*1000, ARM_PLL_CLOCK = 1333333*1000,
DDR_PLL_CLOCK = 1066667*1000, DDR_PLL_CLOCK = 1066667*1000,

17
lib/mk/spec/zynq_parallella/bootstrap-hw.mk
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@@ -1,7 +1,14 @@
TMP := $(call select_from_repositories,lib/mk/spec/zynq/bootstrap-hw.inc) TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/bootstrap-hw.inc=%) BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1 INC_DIR += $(BASE_HW_DIR)/src/bootstrap/spec/zynq
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_parallella
include $(BASE_HW_DIR)/lib/mk/spec/zynq/bootstrap-hw.inc SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/zynq/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc

1
lib/mk/spec/zynq_parallella/core-hw.mk
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@@ -8,7 +8,6 @@ TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%) BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
# add include paths # add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_parallella INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_parallella
# include less specific configuration # include less specific configuration

17
lib/mk/spec/zynq_zc702/bootstrap-hw.mk
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@@ -1,7 +1,14 @@
TMP := $(call select_from_repositories,lib/mk/spec/zynq/bootstrap-hw.inc) TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/bootstrap-hw.inc=%) BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1 INC_DIR += $(BASE_HW_DIR)/src/bootstrap/spec/zynq
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc702
include $(BASE_HW_DIR)/lib/mk/spec/zynq/bootstrap-hw.inc SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/zynq/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc

1
lib/mk/spec/zynq_zc702/core-hw.mk
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@@ -8,7 +8,6 @@ TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%) BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
# add include paths # add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc702 INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc702
# include less specific configuration # include less specific configuration

17
lib/mk/spec/zynq_zc706/bootstrap-hw.mk
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@@ -1,7 +1,14 @@
TMP := $(call select_from_repositories,lib/mk/spec/zynq/bootstrap-hw.inc) TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/bootstrap-hw.inc=%) BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1 INC_DIR += $(BASE_HW_DIR)/src/bootstrap/spec/zynq
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc706
include $(BASE_HW_DIR)/lib/mk/spec/zynq/bootstrap-hw.inc SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/zynq/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc

1
lib/mk/spec/zynq_zc706/core-hw.mk
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@@ -8,7 +8,6 @@ TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%) BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
# add include paths # add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc706 INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc706
# include less specific configuration # include less specific configuration

17
lib/mk/spec/zynq_zedboard/bootstrap-hw.mk
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@@ -1,7 +1,14 @@
TMP := $(call select_from_repositories,lib/mk/spec/zynq/bootstrap-hw.inc) TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/bootstrap-hw.inc=%) BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1 INC_DIR += $(BASE_HW_DIR)/src/bootstrap/spec/zynq
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zedboard
include $(BASE_HW_DIR)/lib/mk/spec/zynq/bootstrap-hw.inc SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/zynq/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
include $(BASE_HW_DIR)/lib/mk/bootstrap-hw.inc

1
lib/mk/spec/zynq_zedboard/core-hw.mk
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@@ -8,7 +8,6 @@ TMP := $(call select_from_repositories,lib/mk/spec/zynq/core-hw.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%) BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core-hw.inc=%)
# add include paths # add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zedboard INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zedboard
# include less specific configuration # include less specific configuration

3
mk/spec/zynq_parallella.mk
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@@ -3,7 +3,4 @@
# #
SPECS += zynq cadence_gem zynq_sdhci SPECS += zynq cadence_gem zynq_sdhci
REP_INC_DIR += include/spec/parallella
REP_INC_DIR += include/spec/xilinx
include $(call select_from_repositories,mk/spec/zynq.mk) include $(call select_from_repositories,mk/spec/zynq.mk)

3
mk/spec/zynq_zc702.mk
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@@ -3,7 +3,4 @@
# #
SPECS += zynq cadence_gem zynq_sdhci SPECS += zynq cadence_gem zynq_sdhci
REP_INC_DIR += include/spec/zc702
REP_INC_DIR += include/spec/xilinx
include $(call select_from_repositories,mk/spec/zynq.mk) include $(call select_from_repositories,mk/spec/zynq.mk)

3
mk/spec/zynq_zc706.mk
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@@ -3,7 +3,4 @@
# #
SPECS += zynq cadence_gem zynq_sdhci SPECS += zynq cadence_gem zynq_sdhci
REP_INC_DIR += include/spec/zc706
REP_INC_DIR += include/spec/xilinx
include $(call select_from_repositories,mk/spec/zynq.mk) include $(call select_from_repositories,mk/spec/zynq.mk)

3
mk/spec/zynq_zedboard.mk
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@@ -3,7 +3,4 @@
# #
SPECS += zynq cadence_gem zynq_i2c SPECS += zynq cadence_gem zynq_i2c
REP_INC_DIR += include/spec/zedboard
REP_INC_DIR += include/spec/xilinx
include $(call select_from_repositories,mk/spec/zynq.mk) include $(call select_from_repositories,mk/spec/zynq.mk)

45
src/core/include/spec/xilinx_uartps_1/serial.h
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@@ -1,45 +0,0 @@
/*
* \brief Serial output driver for core
* \author Johannes Schlatow
* \date 2014-12-15
*/
/*
* Copyright (C) 2014-2015 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _CORE__INCLUDE__SPEC__XILINX_UARTPS_1__SERIAL_H_
#define _CORE__INCLUDE__SPEC__XILINX_UARTPS_1__SERIAL_H_
/* core includes */
#include <board.h>
#include <platform.h>
/* Genode includes */
#include <drivers/uart_base.h>
namespace Genode { class Serial; }
/**
* Serial output driver for core
*/
class Genode::Serial : public Xilinx_uartps_base
{
public:
/**
* Constructor
*
* \param baud_rate targeted transfer baud-rate
*/
Serial(unsigned const baud_rate)
:
Xilinx_uartps_base(Platform::mmio_to_virt(Board::UART_1_MMIO_BASE),
Board::UART_CLOCK, baud_rate)
{ }
};
#endif /* _CORE__INCLUDE__SPEC__XILINX_UARTPS_1__SERIAL_H_ */

28
src/core/include/spec/zynq_parallella/board.h
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@@ -7,27 +7,35 @@
*/ */
/* /*
* Copyright (C) 2014-2015 Genode Labs GmbH * Copyright (C) 2014-2017 Genode Labs GmbH
* *
* This file is part of the Genode OS framework, which is distributed * This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _CORE__INCLUDE__SPEC__ZYNQ_PARALLELLA__BOARD_H_ #ifndef _CORE__INCLUDE__SPEC__ZYNQ_PARALLELLA__BOARD_H_
#define _CORE__INCLUDE__SPEC__ZYNQ_PARALLELLA__BOARD_H_ #define _CORE__INCLUDE__SPEC__ZYNQ_PARALLELLA__BOARD_H_
/* core includes */ /* core includes */
#include <spec/cortex_a9/board_support.h> #include <drivers/defs/zynq_parallella.h>
#include <drivers/uart/xilinx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Board {
using namespace Zynq_parallella;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
using Serial = Genode::Xilinx_uart;
namespace Genode
{
struct Board : Cortex_a9::Board
{
enum { enum {
KERNEL_UART_BASE = UART_1_MMIO_BASE, UART_BASE = UART_1_MMIO_BASE,
KERNEL_UART_SIZE = UART_SIZE,
};
}; };
static constexpr bool SMP = true;
L2_cache & l2_cache();
} }
#endif /* _CORE__INCLUDE__SPEC__ZYNQ_PARALLELLA__BOARD_H_ */ #endif /* _CORE__INCLUDE__SPEC__ZYNQ_PARALLELLA__BOARD_H_ */

28
src/core/include/spec/zynq_zc702/board.h
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@@ -7,27 +7,35 @@
*/ */
/* /*
* Copyright (C) 2014-2015 Genode Labs GmbH * Copyright (C) 2014-2017 Genode Labs GmbH
* *
* This file is part of the Genode OS framework, which is distributed * This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _CORE__INCLUDE__SPEC__ZYNQ_ZC702__BOARD_H_ #ifndef _CORE__INCLUDE__SPEC__ZYNQ_ZC702__BOARD_H_
#define _CORE__INCLUDE__SPEC__ZYNQ_ZC702__BOARD_H_ #define _CORE__INCLUDE__SPEC__ZYNQ_ZC702__BOARD_H_
/* core includes */ /* core includes */
#include <spec/cortex_a9/board_support.h> #include <drivers/defs/zynq_zc702.h>
#include <drivers/uart/xilinx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Board {
using namespace Zynq_zc702;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
using Serial = Genode::Xilinx_uart;
namespace Genode
{
struct Board : Cortex_a9::Board
{
enum { enum {
KERNEL_UART_BASE = UART_1_MMIO_BASE, UART_BASE = UART_1_MMIO_BASE,
KERNEL_UART_SIZE = UART_SIZE,
};
}; };
static constexpr bool SMP = true;
L2_cache & l2_cache();
} }
#endif /* _CORE__INCLUDE__SPEC__ZYNQ_ZC702__BOARD_H_ */ #endif /* _CORE__INCLUDE__SPEC__ZYNQ_ZC702__BOARD_H_ */

28
src/core/include/spec/zynq_zc706/board.h
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@@ -7,27 +7,35 @@
*/ */
/* /*
* Copyright (C) 2014-2015 Genode Labs GmbH * Copyright (C) 2014-2017 Genode Labs GmbH
* *
* This file is part of the Genode OS framework, which is distributed * This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _CORE__INCLUDE__SPEC__ZYNQ_ZC706__BOARD_H_ #ifndef _CORE__INCLUDE__SPEC__ZYNQ_ZC706__BOARD_H_
#define _CORE__INCLUDE__SPEC__ZYNQ_ZC706__BOARD_H_ #define _CORE__INCLUDE__SPEC__ZYNQ_ZC706__BOARD_H_
/* core includes */ /* core includes */
#include <spec/cortex_a9/board_support.h> #include <drivers/defs/zynq_zc706.h>
#include <drivers/uart/xilinx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Board {
using namespace Zynq_zc706;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
using Serial = Genode::Xilinx_uart;
namespace Genode
{
struct Board : Cortex_a9::Board
{
enum { enum {
KERNEL_UART_BASE = UART_1_MMIO_BASE, UART_BASE = UART_1_MMIO_BASE,
KERNEL_UART_SIZE = UART_SIZE,
};
}; };
static constexpr bool SMP = true;
L2_cache & l2_cache();
} }
#endif /* _CORE__INCLUDE__SPEC__ZYNQ_ZC706__BOARD_H_ */ #endif /* _CORE__INCLUDE__SPEC__ZYNQ_ZC706__BOARD_H_ */

28
src/core/include/spec/zynq_zedboard/board.h
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@@ -7,27 +7,35 @@
*/ */
/* /*
* Copyright (C) 2014-2015 Genode Labs GmbH * Copyright (C) 2014-2017 Genode Labs GmbH
* *
* This file is part of the Genode OS framework, which is distributed * This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _CORE__INCLUDE__SPEC__ZYNQ_ZEDBOARD__BOARD_H_ #ifndef _CORE__INCLUDE__SPEC__ZYNQ_ZEDBOARD__BOARD_H_
#define _CORE__INCLUDE__SPEC__ZYNQ_ZEDBOARD__BOARD_H_ #define _CORE__INCLUDE__SPEC__ZYNQ_ZEDBOARD__BOARD_H_
/* core includes */ /* core includes */
#include <spec/cortex_a9/board_support.h> #include <drivers/defs/zynq_zedboard.h>
#include <drivers/uart/xilinx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Board {
using namespace Zynq_zedboard;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
using Serial = Genode::Xilinx_uart;
namespace Genode
{
struct Board : Cortex_a9::Board
{
enum { enum {
KERNEL_UART_BASE = UART_1_MMIO_BASE, UART_BASE = UART_1_MMIO_BASE,
KERNEL_UART_SIZE = UART_SIZE,
};
}; };
static constexpr bool SMP = true;
L2_cache & l2_cache();
} }
#endif /* _CORE__INCLUDE__SPEC__ZYNQ_ZEDBOARD__BOARD_H_ */ #endif /* _CORE__INCLUDE__SPEC__ZYNQ_ZEDBOARD__BOARD_H_ */