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zynq: update to 17.05

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Ref #74
This commit is contained in:
Johannes Schlatow
2017-08-07 17:29:33 +02:00
committed by Norman Feske
parent 834f98137f
commit 98820ffab4
21 changed files with 153 additions and 169 deletions
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41
include/drivers/defs/zynq_parallella.h Normal file
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/*
* \brief Base driver for Parallella Board
* \author Johannes Schlatow
* \date 2015-06-30
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_
#include <drivers/defs/zynq.h>
namespace Zynq_parallella {
using namespace Zynq;
enum {
/* clocks (assuming 6:2:1 mode) */
PS_CLOCK = 33333333,
CPU_1X_CLOCK = 111111100,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
SDHCI_BASE = MMIO_0_BASE + 0x101000,
SDHCI_SIZE = 0x100,
SDHCI_IRQ = 79,
UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
};
};
#endif /* _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_ */

40
include/drivers/defs/zynq_zc702.h Normal file
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/*
* \brief Base driver for ZC702 Board
* \author Johannes Schlatow
* \date 2016-03-24
*/
/*
* Copyright (C) 2016-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_
#include <drivers/defs/zynq.h>
namespace Zynq_zc702 {
using namespace Zynq;
enum {
/* clocks (assuming 6:2:1 mode) */
CPU_1X_CLOCK = 111111100,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
SDHCI_BASE = MMIO_0_BASE + 0x100000,
SDHCI_SIZE = 0x100,
SDHCI_IRQ = 56,
UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
};
};
#endif /* _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_ */

40
include/drivers/defs/zynq_zc706.h Normal file
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/*
* \brief Base driver for ZC706 Board
* \author Johannes Schlatow
* \date 2016-03-24
*/
/*
* Copyright (C) 2016-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_
#include <drivers/defs/zynq.h>
namespace Zynq_zc706 {
using namespace Zynq;
enum {
/* clocks (assuming 6:2:1 mode) */
CPU_1X_CLOCK = 111111100,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
SDHCI_BASE = MMIO_0_BASE + 0x100000,
SDHCI_SIZE = 0x100,
SDHCI_IRQ = 56,
UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
};
};
#endif /* _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_ */

61
include/drivers/defs/zynq_zedboard.h Normal file
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/*
* \brief Base driver for Zedboard
* \author Mark Albers
* \date 2015-09-29
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_
#include <drivers/defs/zynq.h>
namespace Zynq_zedboard {
using namespace Zynq;
enum {
/* clocks (assuming 6:2:1 mode) */
PS_CLOCK = 33333333,
ARM_PLL_CLOCK = 1333333*1000,
DDR_PLL_CLOCK = 1066667*1000,
IO_PLL_CLOCK = 1000*1000*1000,
CPU_1X_CLOCK = 111111115,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
CPU_3X2X_CLOCK = 3*CPU_1X_CLOCK,
CPU_2X_CLOCK = 2*CPU_1X_CLOCK,
UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
RAM_0_SIZE = 0x20000000, /* 512MB */
DDR_CLOCK = 533333313,
FCLK_CLK0 = 100*1000*1000, /* AXI */
FCLK_CLK1 = 20250*1000, /* Cam */
FCLK_CLK2 = 150*1000*1000, /* AXI HP */
I2C0_MMIO_BASE = 0xE0004000,
I2C1_MMIO_BASE = 0xE0005000,
I2C_MMIO_SIZE = 0x1000,
QSPI_CLOCK = 200*1000*1000,
ETH_CLOCK = 125*1000*1000,
SD_CLOCK = 50*1000*1000,
GPIO_MMIO_SIZE = 0x1000,
VDMA_MMIO_SIZE = 0x10000,
};
};
#endif /* _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_ */