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zynq: add specs for zynq-based boards

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- zynq_parallella
- zynq_zedboard
- zynq_zc706
- zynq_zc702
This commit is contained in:
Johannes Schlatow
2016-03-24 14:52:10 +01:00
committed by Norman Feske
parent 7f61d9a84a
commit 2e7bb650dc
17 changed files with 469 additions and 0 deletions
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45
include/spec/parallella/drivers/board_base.h Normal file
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/*
* \brief Base driver for Parallella Board
* \author Johannes Schlatow
* \date 2015-06-30
*/
/*
* Copyright (C) 2015 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_
#include <spec/zynq/drivers/board_base_support.h>
namespace Genode { struct Board_base; }
/**
* Base driver for the Parallella platform
*/
struct Genode::Board_base : Zynq::Board_base
{
enum
{
/* clocks (assuming 6:2:1 mode) */
PS_CLOCK = 33333333,
CPU_1X_CLOCK = 111111100,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
SDHCI_BASE = MMIO_0_BASE + 0x101000,
SDHCI_SIZE = 0x100,
SDHCI_IRQ = 79,
UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
};
};
#endif /* _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_ */

44
include/spec/zc702/drivers/board_base.h Normal file
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/*
* \brief Base driver for ZC702 Board
* \author Johannes Schlatow
* \date 2016-03-24
*/
/*
* Copyright (C) 2016 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_
#include <spec/zynq/drivers/board_base_support.h>
namespace Genode { struct Board_base; }
/**
* Base driver for the ZC702 platform
*/
struct Genode::Board_base : Zynq::Board_base
{
enum
{
/* clocks (assuming 6:2:1 mode) */
CPU_1X_CLOCK = 111111100,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
SDHCI_BASE = MMIO_0_BASE + 0x100000,
SDHCI_SIZE = 0x100,
SDHCI_IRQ = 56,
UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
};
};
#endif /* _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_ */

44
include/spec/zc706/drivers/board_base.h Normal file
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/*
* \brief Base driver for ZC706 Board
* \author Johannes Schlatow
* \date 2016-03-24
*/
/*
* Copyright (C) 2016 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_
#include <spec/zynq/drivers/board_base_support.h>
namespace Genode { struct Board_base; }
/**
* Base driver for the ZC706 platform
*/
struct Genode::Board_base : Zynq::Board_base
{
enum
{
/* clocks (assuming 6:2:1 mode) */
CPU_1X_CLOCK = 111111100,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
SDHCI_BASE = MMIO_0_BASE + 0x100000,
SDHCI_SIZE = 0x100,
SDHCI_IRQ = 56,
UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
};
};
#endif /* _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_ */

64
include/spec/zedboard/drivers/board_base.h Normal file
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/*
* \brief Base driver for Zedboard
* \author Mark Albers
* \date 2015-09-29
*/
/*
* Copyright (C) 2015 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_
#include <spec/zynq/drivers/board_base_support.h>
namespace Genode { struct Board_base; }
/**
* Base driver for the Zedboard platform
*/
struct Genode::Board_base : Zynq::Board_base
{
enum
{
PS_CLOCK = 33333333,
ARM_PLL_CLOCK = 1333333*1000,
DDR_PLL_CLOCK = 1066667*1000,
IO_PLL_CLOCK = 1000*1000*1000,
CPU_1X_CLOCK = 111111115,
CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
CPU_3X2X_CLOCK = 3*CPU_1X_CLOCK,
CPU_2X_CLOCK = 2*CPU_1X_CLOCK,
UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
RAM_0_SIZE = 0x20000000, /* 512MB */
DDR_CLOCK = 533333313,
FCLK_CLK0 = 100*1000*1000, /* AXI */
FCLK_CLK1 = 20250*1000, /* Cam */
FCLK_CLK2 = 150*1000*1000, /* AXI HP */
I2C0_MMIO_BASE = 0xE0004000,
I2C1_MMIO_BASE = 0xE0005000,
I2C_MMIO_SIZE = 0x1000,
QSPI_CLOCK = 200*1000*1000,
ETH_CLOCK = 125*1000*1000,
SD_CLOCK = 50*1000*1000,
GPIO_MMIO_SIZE = 0x1000,
VDMA_MMIO_SIZE = 0x10000,
};
};
#endif /* _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_ */

15
lib/mk/spec/zynq_parallella/core.mk Normal file
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#
# \brief Build config for Genodes core process
# \author Johannes Schlatow
# \date 2016-05-03
#
TMP := $(call select_from_repositories,lib/mk/spec/zynq/core.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core.inc=%)
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_parallella
# include less specific configuration
include $(BASE_HW_DIR)/lib/mk/spec/zynq/core.inc

15
lib/mk/spec/zynq_zc702/core.mk Normal file
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#
# \brief Build config for Genodes core process
# \author Johannes Schlatow
# \date 2016-05-03
#
TMP := $(call select_from_repositories,lib/mk/spec/zynq/core.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core.inc=%)
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc702
# include less specific configuration
include $(BASE_HW_DIR)/lib/mk/spec/zynq/core.inc

15
lib/mk/spec/zynq_zc706/core.mk Normal file
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#
# \brief Build config for Genodes core process
# \author Johannes Schlatow
# \date 2016-05-03
#
TMP := $(call select_from_repositories,lib/mk/spec/zynq/core.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core.inc=%)
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zc706
# include less specific configuration
include $(BASE_HW_DIR)/lib/mk/spec/zynq/core.inc

15
lib/mk/spec/zynq_zedboard/core.mk Normal file
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#
# \brief Build config for Genodes core process
# \author Johannes Schlatow
# \date 2016-05-03
#
TMP := $(call select_from_repositories,lib/mk/spec/zynq/core.inc)
BASE_HW_DIR := $(TMP:%lib/mk/spec/zynq/core.inc=%)
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_1
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_zedboard
# include less specific configuration
include $(BASE_HW_DIR)/lib/mk/spec/zynq/core.inc

9
mk/spec/zynq_parallella.mk Normal file
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#
# Pull in CPU specifics
#
SPECS += zynq cadence_gem
REP_INC_DIR += include/spec/parallella
REP_INC_DIR += include/spec/xilinx
include $(call select_from_repositories,mk/spec/zynq.mk)

9
mk/spec/zynq_zc702.mk Normal file
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#
# Pull in CPU specifics
#
SPECS += zynq cadence_gem zynq_uart1
REP_INC_DIR += include/spec/zc702
REP_INC_DIR += include/spec/xilinx
include $(call select_from_repositories,mk/spec/zynq.mk)

9
mk/spec/zynq_zc706.mk Normal file
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#
# Pull in CPU specifics
#
SPECS += zynq cadence_gem zynq_uart1
REP_INC_DIR += include/spec/zc706
REP_INC_DIR += include/spec/xilinx
include $(call select_from_repositories,mk/spec/zynq.mk)

9
mk/spec/zynq_zedboard.mk Normal file
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#
# Pull in CPU specifics
#
SPECS += zynq cadence_gem zynq_uart1
REP_INC_DIR += include/spec/zedboard
REP_INC_DIR += include/spec/xilinx
include $(call select_from_repositories,mk/spec/zynq.mk)

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src/core/include/spec/xilinx_uartps_1/serial.h Normal file
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/*
* \brief Serial output driver for core
* \author Johannes Schlatow
* \date 2014-12-15
*/
/*
* Copyright (C) 2014-2015 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _CORE__INCLUDE__SPEC__XILINX_UARTPS_1__SERIAL_H_
#define _CORE__INCLUDE__SPEC__XILINX_UARTPS_1__SERIAL_H_
/* core includes */
#include <board.h>
/* Genode includes */
#include <drivers/uart_base.h>
namespace Genode { class Serial; }
/**
* Serial output driver for core
*/
class Genode::Serial : public Xilinx_uartps_base
{
public:
/**
* Constructor
*
* \param baud_rate targeted transfer baud-rate
*/
Serial(unsigned const baud_rate)
:
Xilinx_uartps_base(Board::UART_1_MMIO_BASE,
Board::UART_CLOCK, baud_rate)
{ }
};
#endif /* _CORE__INCLUDE__SPEC__XILINX_UARTPS_1__SERIAL_H_ */

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src/core/include/spec/zynq_parallella/board.h Normal file
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/*
* \brief Board driver for core on Zynq
* \author Johannes Schlatow
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2014-06-02
*/
/*
* Copyright (C) 2014-2015 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _CORE__INCLUDE__SPEC__ZYNQ_PARALLELLA__BOARD_H_
#define _CORE__INCLUDE__SPEC__ZYNQ_PARALLELLA__BOARD_H_
/* core includes */
#include <spec/cortex_a9/board_support.h>
namespace Genode
{
struct Board : Cortex_a9::Board
{
enum {
KERNEL_UART_BASE = UART_1_MMIO_BASE,
KERNEL_UART_SIZE = UART_SIZE,
};
};
}
#endif /* _CORE__INCLUDE__SPEC__ZYNQ_PARALLELLA__BOARD_H_ */

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src/core/include/spec/zynq_zc702/board.h Normal file
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/*
* \brief Board driver for core on Zynq
* \author Johannes Schlatow
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2014-06-02
*/
/*
* Copyright (C) 2014-2015 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _CORE__INCLUDE__SPEC__ZYNQ_ZC702__BOARD_H_
#define _CORE__INCLUDE__SPEC__ZYNQ_ZC702__BOARD_H_
/* core includes */
#include <spec/cortex_a9/board_support.h>
namespace Genode
{
struct Board : Cortex_a9::Board
{
enum {
KERNEL_UART_BASE = UART_1_MMIO_BASE,
KERNEL_UART_SIZE = UART_SIZE,
};
};
}
#endif /* _CORE__INCLUDE__SPEC__ZYNQ_ZC702__BOARD_H_ */

33
src/core/include/spec/zynq_zc706/board.h Normal file
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/*
* \brief Board driver for core on Zynq
* \author Johannes Schlatow
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2014-06-02
*/
/*
* Copyright (C) 2014-2015 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _CORE__INCLUDE__SPEC__ZYNQ_ZC706__BOARD_H_
#define _CORE__INCLUDE__SPEC__ZYNQ_ZC706__BOARD_H_
/* core includes */
#include <spec/cortex_a9/board_support.h>
namespace Genode
{
struct Board : Cortex_a9::Board
{
enum {
KERNEL_UART_BASE = UART_1_MMIO_BASE,
KERNEL_UART_SIZE = UART_SIZE,
};
};
}
#endif /* _CORE__INCLUDE__SPEC__ZYNQ_ZC706__BOARD_H_ */

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src/core/include/spec/zynq_zedboard/board.h Normal file
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/*
* \brief Board driver for core on Zynq
* \author Johannes Schlatow
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2014-06-02
*/
/*
* Copyright (C) 2014-2015 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _CORE__INCLUDE__SPEC__ZYNQ_ZEDBOARD__BOARD_H_
#define _CORE__INCLUDE__SPEC__ZYNQ_ZEDBOARD__BOARD_H_
/* core includes */
#include <spec/cortex_a9/board_support.h>
namespace Genode
{
struct Board : Cortex_a9::Board
{
enum {
KERNEL_UART_BASE = UART_1_MMIO_BASE,
KERNEL_UART_SIZE = UART_SIZE,
};
};
}
#endif /* _CORE__INCLUDE__SPEC__ZYNQ_ZEDBOARD__BOARD_H_ */