zynq: add specs for zynq-based boards
- zynq_parallella - zynq_zedboard - zynq_zc706 - zynq_zc702
This commit is contained in:
Johannes Schlatow
committed by
Norman Feske
Norman Feske
parent
7f61d9a84a
commit
2e7bb650dc
45
include/spec/parallella/drivers/board_base.h
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45
include/spec/parallella/drivers/board_base.h
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/*
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* \brief Base driver for Parallella Board
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* \author Johannes Schlatow
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* \date 2015-06-30
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_
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#define _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_
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#include <spec/zynq/drivers/board_base_support.h>
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namespace Genode { struct Board_base; }
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/**
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* Base driver for the Parallella platform
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*/
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struct Genode::Board_base : Zynq::Board_base
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{
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enum
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{
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/* clocks (assuming 6:2:1 mode) */
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PS_CLOCK = 33333333,
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CPU_1X_CLOCK = 111111100,
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CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
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CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
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CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
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CORTEX_A9_PRIVATE_TIMER_DIV = 100,
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SDHCI_BASE = MMIO_0_BASE + 0x101000,
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SDHCI_SIZE = 0x100,
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SDHCI_IRQ = 79,
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UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
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};
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};
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#endif /* _INCLUDE__PARALLELLA__DRIVERS__BOARD_BASE_H_ */
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44
include/spec/zc702/drivers/board_base.h
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include/spec/zc702/drivers/board_base.h
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/*
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* \brief Base driver for ZC702 Board
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* \author Johannes Schlatow
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* \date 2016-03-24
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*/
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/*
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* Copyright (C) 2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_
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#define _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_
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#include <spec/zynq/drivers/board_base_support.h>
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namespace Genode { struct Board_base; }
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/**
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* Base driver for the ZC702 platform
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*/
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struct Genode::Board_base : Zynq::Board_base
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{
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enum
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{
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/* clocks (assuming 6:2:1 mode) */
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CPU_1X_CLOCK = 111111100,
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CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
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CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
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CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
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CORTEX_A9_PRIVATE_TIMER_DIV = 100,
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SDHCI_BASE = MMIO_0_BASE + 0x100000,
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SDHCI_SIZE = 0x100,
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SDHCI_IRQ = 56,
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UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
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};
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};
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#endif /* _INCLUDE__ZC702__DRIVERS__BOARD_BASE_H_ */
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44
include/spec/zc706/drivers/board_base.h
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include/spec/zc706/drivers/board_base.h
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/*
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* \brief Base driver for ZC706 Board
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* \author Johannes Schlatow
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* \date 2016-03-24
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*/
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/*
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* Copyright (C) 2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_
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#define _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_
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#include <spec/zynq/drivers/board_base_support.h>
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namespace Genode { struct Board_base; }
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/**
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* Base driver for the ZC706 platform
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*/
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struct Genode::Board_base : Zynq::Board_base
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{
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enum
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{
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/* clocks (assuming 6:2:1 mode) */
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CPU_1X_CLOCK = 111111100,
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CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
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CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
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CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
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CORTEX_A9_PRIVATE_TIMER_DIV = 100,
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SDHCI_BASE = MMIO_0_BASE + 0x100000,
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SDHCI_SIZE = 0x100,
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SDHCI_IRQ = 56,
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UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
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};
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};
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#endif /* _INCLUDE__ZC706__DRIVERS__BOARD_BASE_H_ */
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64
include/spec/zedboard/drivers/board_base.h
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64
include/spec/zedboard/drivers/board_base.h
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/*
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* \brief Base driver for Zedboard
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* \author Mark Albers
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* \date 2015-09-29
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_
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#define _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_
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#include <spec/zynq/drivers/board_base_support.h>
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namespace Genode { struct Board_base; }
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/**
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* Base driver for the Zedboard platform
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*/
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struct Genode::Board_base : Zynq::Board_base
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{
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enum
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{
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PS_CLOCK = 33333333,
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ARM_PLL_CLOCK = 1333333*1000,
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DDR_PLL_CLOCK = 1066667*1000,
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IO_PLL_CLOCK = 1000*1000*1000,
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CPU_1X_CLOCK = 111111115,
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CPU_6X4X_CLOCK = 6*CPU_1X_CLOCK,
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CPU_3X2X_CLOCK = 3*CPU_1X_CLOCK,
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CPU_2X_CLOCK = 2*CPU_1X_CLOCK,
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UART_1_MMIO_BASE = MMIO_0_BASE + UART_SIZE,
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CORTEX_A9_CLOCK = CPU_6X4X_CLOCK,
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CORTEX_A9_PRIVATE_TIMER_CLK = CORTEX_A9_CLOCK,
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CORTEX_A9_PRIVATE_TIMER_DIV = 100,
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RAM_0_SIZE = 0x20000000, /* 512MB */
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DDR_CLOCK = 533333313,
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FCLK_CLK0 = 100*1000*1000, /* AXI */
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FCLK_CLK1 = 20250*1000, /* Cam */
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FCLK_CLK2 = 150*1000*1000, /* AXI HP */
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I2C0_MMIO_BASE = 0xE0004000,
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I2C1_MMIO_BASE = 0xE0005000,
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I2C_MMIO_SIZE = 0x1000,
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QSPI_CLOCK = 200*1000*1000,
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ETH_CLOCK = 125*1000*1000,
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SD_CLOCK = 50*1000*1000,
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GPIO_MMIO_SIZE = 0x1000,
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VDMA_MMIO_SIZE = 0x10000,
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};
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};
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#endif /* _INCLUDE__ZEDBOARD__DRIVERS__BOARD_BASE_H_ */
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