5c4fd5671f
With this patch the comport are tried to read out from the BIOS Data Area on x86 machines. The BDA Area are part of the first physical page and may contain the non-default io ports of the comport. When used together with 'bender' from the 'morbo' toolchain, even serial PCI cards (also Intel's AMT Serial Over Line adapter) are detected automatically.
903 lines
19 KiB
C++
903 lines
19 KiB
C++
#include "support.h"
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#include "startup.h"
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#include <l4/drivers/uart_16550.h>
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#include <l4/drivers/io_regblock_port.h>
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#include <string.h>
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#include "base_critical.h"
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#include "panic.h"
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#include <l4/util/cpu.h>
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#include <l4/util/port_io.h>
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#include <l4/cxx/static_container>
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#include <cassert>
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#include <cstdio>
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/** VGA console output */
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static void vga_init()
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{
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/* Reset any scrolling */
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l4util_out32(0xc, 0x3d4);
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l4util_out32(0, 0x3d5);
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l4util_out32(0xd, 0x3d4);
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l4util_out32(0, 0x3d5);
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}
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static void vga_putchar(unsigned char c)
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{
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static int ofs = -1, esc, esc_val, attr = 0x07;
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unsigned char *vidbase = (unsigned char*)0xb8000;
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base_critical_enter();
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if (ofs < 0)
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{
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/* Called for the first time - initialize. */
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ofs = 80*2*24;
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vga_putchar('\n');
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}
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switch (esc)
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{
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case 1:
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if (c == '[')
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{
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esc++;
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goto done;
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}
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esc = 0;
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break;
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case 2:
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if (c >= '0' && c <= '9')
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{
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esc_val = 10*esc_val + c - '0';
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goto done;
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}
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if (c == 'm')
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{
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attr = esc_val ? 0x0f : 0x07;
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goto done;
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}
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esc = 0;
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break;
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}
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switch (c)
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{
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case '\n':
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memmove(vidbase, vidbase+80*2, 80*2*24);
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memset(vidbase+80*2*24, 0, 80*2);
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/* fall through... */
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case '\r':
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ofs = 0;
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break;
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case '\t':
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ofs = (ofs + 8) & ~7;
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break;
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case '\033':
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esc = 1;
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esc_val = 0;
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break;
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default:
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/* Wrap if we reach the end of a line. */
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if (ofs >= 80)
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vga_putchar('\n');
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/* Stuff the character into the video buffer. */
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{
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volatile unsigned char *p = vidbase + 80*2*24 + ofs*2;
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p[0] = c;
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p[1] = attr;
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ofs++;
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}
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break;
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}
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done:
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base_critical_leave();
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}
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/** Poor man's getchar, only returns raw scan code. We don't need to know
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* _which_ key was pressed, we only want to know _if_ a key was pressed. */
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static int raw_keyboard_getscancode(void)
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{
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unsigned status, scan_code;
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base_critical_enter();
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l4util_cpu_pause();
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/* Wait until a scan code is ready and read it. */
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status = l4util_in8(0x64);
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if ((status & 0x01) == 0)
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{
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base_critical_leave();
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return -1;
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}
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scan_code = l4util_in8(0x60);
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/* Drop mouse events */
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if ((status & 0x20) != 0)
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{
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base_critical_leave();
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return -1;
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}
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base_critical_leave();
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return scan_code;
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}
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static inline l4_uint32_t
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pci_conf_addr(l4_uint32_t bus, l4_uint32_t dev, l4_uint32_t fn, l4_uint32_t reg)
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{ return 0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3); }
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static l4_uint32_t pci_read(unsigned char bus, l4_uint32_t dev,
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l4_uint32_t fn, l4_uint32_t reg,
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unsigned char width)
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{
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l4util_out32(pci_conf_addr(bus, dev, fn, reg), 0xcf8);
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switch (width)
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{
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case 8: return l4util_in8(0xcfc + (reg & 3));
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case 16: return l4util_in16((0xcfc + (reg & 3)) & ~1UL);
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case 32: return l4util_in32(0xcfc);
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}
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return 0;
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}
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static void pci_write(unsigned char bus, l4_uint32_t dev,
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l4_uint32_t fn, l4_uint32_t reg,
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l4_uint32_t val, unsigned char width)
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{
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l4util_out32(pci_conf_addr(bus, dev, fn, reg), 0xcf8);
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switch (width)
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{
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case 8: l4util_out8(val, 0xcfc + (reg & 3)); break;
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case 16: l4util_out16(val, (0xcfc + (reg & 3)) & ~1UL); break;
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case 32: l4util_out32(val, 0xcfc); break;
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}
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}
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namespace {
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struct Resource
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{
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enum Type { NO_BAR, IO_BAR, MEM_BAR };
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Type type;
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unsigned long base;
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unsigned long len;
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Resource() : type(NO_BAR) {}
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};
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enum { NUM_BARS = 6 };
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struct Serial_board
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{
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enum Flags
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{
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F_bar_per_port = 0x10,
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};
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unsigned short flags;
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unsigned short base_bar;
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unsigned num_ports;
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unsigned base_baud;
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unsigned port_offset;
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unsigned base_offset;
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unsigned reg_shift;
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Resource bars[NUM_BARS];
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unsigned num_mem_bars() const
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{
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unsigned n = 0;
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for (unsigned i = 0; i < NUM_BARS; ++i)
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if (bars[i].type == Resource::MEM_BAR)
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++n;
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return n;
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}
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unsigned num_io_bars() const
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{
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unsigned n = 0;
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for (unsigned i = 0; i < NUM_BARS; ++i)
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if (bars[i].type == Resource::IO_BAR)
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++n;
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return n;
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}
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int first_io_bar()
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{
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for (unsigned i = 0; i < NUM_BARS; ++i)
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if (bars[i].type == Resource::IO_BAR)
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return i;
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return -1;
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}
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l4_addr_t get_base(unsigned idx) const
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{
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if (idx >= num_ports)
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idx = 0;
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if (flags & F_bar_per_port)
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return bars[base_bar + idx].base + base_offset;
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return bars[base_bar].base + base_offset + port_offset * idx;
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}
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Resource::Type get_type() const
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{ return bars[base_bar].type; }
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};
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struct Pci_iterator
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{
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unsigned bus;
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unsigned dev;
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unsigned func;
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l4_uint32_t vd;
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enum { Max_bus = 20 };
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Pci_iterator() : bus(0), dev(0), func(0) {}
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explicit Pci_iterator(unsigned bus, unsigned dev = 0, unsigned func = 0)
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: bus(bus), dev(dev), func(func) {}
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static Pci_iterator end() { return Pci_iterator(Max_bus, 0, 0); }
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l4_uint32_t pci_read(l4_uint32_t reg, unsigned char width) const
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{ return ::pci_read(bus, dev, func, reg, width); }
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void pci_write(l4_uint32_t reg, l4_uint32_t val, unsigned char width) const
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{ ::pci_write(bus, dev, func, reg, val, width); }
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void enable_io() const
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{
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unsigned cmd = pci_read(4, 16);
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pci_write(4, cmd | 1, 16);
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}
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void enable_mmio() const
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{
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unsigned cmd = pci_read(4, 16);
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pci_write(4, cmd | 2, 16);
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}
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unsigned vendor() const { return vd & 0xffff; }
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unsigned device() const { return vd >> 16; }
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unsigned vendor_device() const { return vd; }
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unsigned classcode() const { return pci_read(0x0b, 8); }
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unsigned subclass() const { return pci_read(0x0a, 8); }
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unsigned prog() const { return pci_read(9, 8); }
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bool operator == (Pci_iterator const &o) const
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{ return bus == o.bus && dev == o.dev && func == o.func; }
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bool operator != (Pci_iterator const &o) const
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{ return !operator == (o); }
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Pci_iterator const &operator ++ ()
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{
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for (; bus < Max_bus;)
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{
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if (func == 0)
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{
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unsigned char hdr_type = pci_read(0xe, 8);
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if (hdr_type & 0x80)
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++func;
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else
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++dev;
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}
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else if (func < 8)
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++func;
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else
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{
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func = 0;
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++dev;
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}
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if (dev >= 32)
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{
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++bus;
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dev = 0;
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func = 0;
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}
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vd = pci_read(0, 32);
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if (vd == 0xffffffff)
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continue;
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return *this;
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}
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dev = 0;
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func = 0;
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return *this;
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}
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};
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#if 0
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if (classcode == 0x06 && subclass == 0x04)
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buses++;
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#endif
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struct Bs_uart : L4::Uart_16550
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{
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union Regs
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{
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cxx::Static_container<L4::Io_register_block_port> io;
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cxx::Static_container<L4::Io_register_block_mmio> mem;
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};
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Resource::Type type;
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bool ok;
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Regs uart_regs;
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Bs_uart(Serial_board *board, unsigned port, unsigned long baudrate)
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: L4::Uart_16550(board->base_baud, 0, 0, 0x8 /* out2 */, 0), ok(false)
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{
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type = board->get_type();
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if (type == Resource::IO_BAR)
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{
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unsigned base = board->get_base(port);
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uart_regs.io.construct(base);
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if (!startup(uart_regs.io))
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{
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printf("Could not find or enable UART\n");
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return;
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}
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}
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if (type == Resource::MEM_BAR)
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{
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l4_addr_t base = board->get_base(port);
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uart_regs.mem.construct(base, board->reg_shift);
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if (!startup(uart_regs.mem))
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{
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printf("Could not find or enable UART\n");
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return;
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}
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}
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if (!change_mode(L4::Uart_16550::MODE_8N1, baudrate))
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{
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printf("Could not find or enable UART\n");
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return;
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}
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ok = true;
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}
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};
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class Dual_uart : public L4::Uart
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{
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private:
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L4::Uart *_u1, *_u2;
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public:
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Dual_uart(L4::Uart *u1)
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: _u1(u1), _u2(0)
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{}
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void set_uart2(L4::Uart *u2)
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{
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_u2 = u2;
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}
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bool startup(L4::Io_register_block const *)
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{
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return true;
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}
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void shutdown()
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{
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_u1->shutdown();
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if (_u2)
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_u2->shutdown();
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}
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~Dual_uart() {}
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#if 0
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bool enable_rx_irq(bool e)
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{
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bool r1 = _u1->enable_rx_irq(e);
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bool r2 = _u2 ? _u2->enable_rx_irq(e) : false;
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return r1 && r2;
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}
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bool enable_tx_irq(bool e)
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{
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bool r1 = _u1->enable_tx_irq(e);
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bool r2 = _u2 ? _u2->enable_tx_irq(e) : false;
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return r1 && r2;
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}
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#endif
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bool change_mode(Transfer_mode m, Baud_rate r)
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{
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bool r1 = _u1->change_mode(m, r);
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bool r2 = _u2 ? _u2->change_mode(m, r) : false;
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return r1 && r2;
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}
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int char_avail() const
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{
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return _u1->char_avail() || (_u2 && _u2->char_avail());
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}
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int get_char(bool blocking) const
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{
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int c;
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do
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{
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c = _u1->get_char(false);
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if (c == -1 && _u2)
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c = _u2->get_char(false);
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}
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while (blocking && c == -1);
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return c;
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}
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int write(char const *s, unsigned long count) const
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{
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int r = _u1->write(s, count);
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if (_u2)
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_u2->write(s, count);
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return r;
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}
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};
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}
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struct Pci_com_drv
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{
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virtual bool setup(Pci_iterator const &i, Serial_board *board) const = 0;
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virtual ~Pci_com_drv() = 0;
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static void read_bars(Pci_iterator const &i, Serial_board *board);
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};
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inline Pci_com_drv::~Pci_com_drv() {}
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void
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Pci_com_drv::read_bars(Pci_iterator const &dev, Serial_board *board)
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{
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for (int bar = 0; bar < NUM_BARS; ++bar)
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{
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int a = 0x10 + bar * 4;
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unsigned v = dev.pci_read(a, 32);
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dev.pci_write(a, ~0U, 32);
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unsigned x = dev.pci_read(a, 32);
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dev.pci_write(a, v, 32);
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if (!v)
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continue;
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int s;
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for (s = 2; s < 32; ++s)
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if ((x >> s) & 1)
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break;
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board->bars[bar].base = v & ~3UL;
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board->bars[bar].len = 1 << s;
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board->bars[bar].type = (v & 1) ? Resource::IO_BAR : Resource::MEM_BAR;
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if (0)
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printf("BAR%d: %04x (sz=%d)\n", bar, v & ~3, 1 << s);
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}
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}
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struct Pci_com_drv_default : Pci_com_drv
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{
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bool setup(Pci_iterator const &dev, Serial_board *board) const
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{
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read_bars(dev, board);
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int num_iobars = board->num_io_bars();
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if (num_iobars != 1)
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return false;
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//int num_membars = board->num_mem_bars();
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//if (num_membars > 1)
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// return false;
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int first_port = board->first_io_bar();
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board->port_offset = 8;
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board->base_baud = L4::Uart_16550::Base_rate_x86;
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board->base_bar = first_port;
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board->num_ports = board->bars[first_port].len / board->port_offset;
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board->flags = 0;
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printf(" detected serial IO card: bar=%d ports=%d\n",
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first_port, board->num_ports);
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dev.enable_io();
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return true;
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}
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};
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struct Pci_com_drv_fallback : Pci_com_drv_default
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{
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bool setup(Pci_iterator const &dev, Serial_board *board) const
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{
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// The default drivers only takes 7:80 typed devices
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if (dev.classcode() != 7)
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return false;
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if (dev.subclass() != 0x80)
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return false;
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return Pci_com_drv_default::setup(dev, board);
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}
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};
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struct Pci_com_drv_oxsemi : Pci_com_drv
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{
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bool setup(Pci_iterator const &dev, Serial_board *board) const
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{
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read_bars(dev, board);
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board->flags = 0;
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board->num_ports = 0;
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switch (dev.device())
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{
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case 0xc158:
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board->num_ports = 2;
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board->base_baud = 4000000;
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board->port_offset = 0x200;
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board->base_bar = 0;
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board->base_offset = 0x1000;
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board->reg_shift = 0;
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break;
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default:
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break;
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}
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if (!board->num_ports)
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return false;
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printf(" found oxsemi PCI controller.\n");
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dev.enable_mmio();
|
|
return true;
|
|
}
|
|
};
|
|
|
|
struct Pci_com_moschip : public Pci_com_drv
|
|
{
|
|
bool setup(Pci_iterator const &dev, Serial_board *board) const
|
|
{
|
|
read_bars(dev, board);
|
|
|
|
int first_port = board->first_io_bar();
|
|
|
|
board->port_offset = 8;
|
|
board->base_baud = L4::Uart_16550::Base_rate_x86;
|
|
board->base_bar = first_port;
|
|
board->num_ports = board->bars[first_port].len / board->port_offset;
|
|
board->flags = 0;
|
|
printf(" detected serial IO card: bar=%d ports=%d\n",
|
|
first_port, board->num_ports);
|
|
dev.enable_io();
|
|
return true;
|
|
}
|
|
|
|
};
|
|
|
|
static Pci_com_drv_fallback _fallback_pci_com;
|
|
static Pci_com_drv_default _default_pci_com;
|
|
static Pci_com_drv_oxsemi _oxsemi_pci_com;
|
|
static Pci_com_moschip _moschip;
|
|
|
|
#define PCI_DEVICE_ID(vendor, device) \
|
|
(((unsigned)(device) << 16) | (unsigned)(vendor & 0xffff)), 0xffffffffU
|
|
#define PCI_ANY_DEVICE 0, 0
|
|
|
|
struct Pci_com_dev
|
|
{
|
|
unsigned vendor_device;
|
|
unsigned mask;
|
|
Pci_com_drv *driver;
|
|
};
|
|
|
|
Pci_com_dev _devs[] = {
|
|
{ PCI_DEVICE_ID(0x1415, 0xc158), &_oxsemi_pci_com },
|
|
{ PCI_DEVICE_ID(0x9710, 0x9835), &_moschip },
|
|
{ PCI_DEVICE_ID(0x9710, 0x9865), &_moschip },
|
|
{ PCI_DEVICE_ID(0x9710, 0x9922), &_moschip },
|
|
{ PCI_DEVICE_ID(0x8086, 0x8c3d), &_default_pci_com },
|
|
{ PCI_ANY_DEVICE, &_fallback_pci_com },
|
|
};
|
|
|
|
enum { Num_known_devs = sizeof(_devs) / sizeof(_devs[0]) };
|
|
|
|
|
|
static Pci_iterator
|
|
_search_pci_serial_devs(Pci_iterator const &begin, Pci_iterator const &end,
|
|
Serial_board *board, bool print)
|
|
{
|
|
for (Pci_iterator i = begin; i != end; ++i)
|
|
{
|
|
if (print)
|
|
printf("%02x:%02x.%1x Class %02x.%02x Prog %02x: %04x:%04x\n",
|
|
i.bus, i.dev, i.func, i.classcode(), i.subclass(), i.prog(),
|
|
i.vendor(), i.device());
|
|
|
|
for (unsigned devs = 0; devs < Num_known_devs; ++devs)
|
|
if ( (i.vendor_device() & _devs[devs].mask) == _devs[devs].vendor_device
|
|
&& _devs[devs].driver->setup(i, board))
|
|
return i;
|
|
}
|
|
|
|
return end;
|
|
}
|
|
|
|
static unsigned long
|
|
search_pci_serial_devs(int card_idx, Serial_board *board)
|
|
{
|
|
Pci_iterator end = Pci_iterator::end();
|
|
Pci_iterator i;
|
|
for (int card = 0; i != end; ++i, ++card) {
|
|
i = _search_pci_serial_devs(i, end, board, false);
|
|
if (card == card_idx)
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
scan_pci_uarts(Dual_uart *du, unsigned long baudrate)
|
|
{
|
|
Serial_board board;
|
|
Pci_iterator end = Pci_iterator::end();
|
|
// classes should be 7:0
|
|
Pci_iterator i;
|
|
for (int card = 0; i != end; ++i, ++card)
|
|
{
|
|
i = _search_pci_serial_devs(i, end, &board, true);
|
|
|
|
if (i == end)
|
|
break;
|
|
|
|
for (unsigned p = 0; p < board.num_ports; ++p)
|
|
{
|
|
printf("probed PCI UART %02x:%02x.%1x\n",
|
|
i.bus, i.dev, i.func);
|
|
Bs_uart u(&board, p, baudrate);
|
|
du->set_uart2(&u);
|
|
printf("probed PCI UART %02x:%02x.%1x\n"
|
|
"to use this port set: -comport=pci:%d:%d\n",
|
|
i.bus, i.dev, i.func, card, p);
|
|
du->set_uart2(0);
|
|
}
|
|
}
|
|
printf("done scanning PCI uarts\n");
|
|
}
|
|
|
|
class Uart_vga : public L4::Uart
|
|
{
|
|
public:
|
|
Uart_vga()
|
|
{ }
|
|
|
|
bool startup(L4::Io_register_block const *)
|
|
{
|
|
vga_init();
|
|
return true;
|
|
}
|
|
|
|
~Uart_vga() {}
|
|
void shutdown() {}
|
|
bool enable_rx_irq(bool) { return false; }
|
|
bool enable_tx_irq(bool) { return false; }
|
|
bool change_mode(Transfer_mode, Baud_rate) { return true; }
|
|
int get_char(bool blocking) const
|
|
{
|
|
int c;
|
|
do
|
|
c = raw_keyboard_getscancode();
|
|
while (blocking && c == -1);
|
|
return c;
|
|
}
|
|
|
|
int char_avail() const
|
|
{
|
|
return raw_keyboard_getscancode() != -1;
|
|
}
|
|
|
|
int write(char const *s, unsigned long count) const
|
|
{
|
|
unsigned long c = count;
|
|
while (c)
|
|
{
|
|
if (*s == 10)
|
|
vga_putchar(13);
|
|
vga_putchar(*s++);
|
|
--c;
|
|
}
|
|
return count;
|
|
}
|
|
};
|
|
|
|
|
|
static void
|
|
legacy_uart(unsigned com_port_or_base, int &com_irq, Serial_board *board)
|
|
{
|
|
switch (com_port_or_base)
|
|
{
|
|
case 1: com_port_or_base = 0x3f8;
|
|
if (com_irq == -1)
|
|
com_irq = 4;
|
|
break;
|
|
case 2: com_port_or_base = 0x2f8;
|
|
if (com_irq == -1)
|
|
com_irq = 3;
|
|
break;
|
|
case 3: com_port_or_base = 0x3e8; break;
|
|
case 4: com_port_or_base = 0x2e8; break;
|
|
}
|
|
|
|
board->num_ports = 1;
|
|
board->bars[0].type = Resource::IO_BAR;
|
|
board->bars[0].base = com_port_or_base;
|
|
board->base_bar = 0;
|
|
board->flags = 0;
|
|
board->base_offset = 0;
|
|
board->port_offset = 8;
|
|
board->base_baud = L4::Uart_16550::Base_rate_x86;
|
|
board->reg_shift = 0;
|
|
}
|
|
|
|
|
|
class Platform_x86 : public Platform_base
|
|
{
|
|
public:
|
|
#ifdef ARCH_amd64
|
|
ptab64_mem_info_t const *ptab64_info;
|
|
#endif
|
|
bool probe() { return true; }
|
|
|
|
int init_uart(Serial_board *board, int port, int com_irq, Dual_uart *du)
|
|
{
|
|
base_critical_enter();
|
|
unsigned baudrate = 115200;
|
|
|
|
static cxx::Static_container<Bs_uart> uart;
|
|
uart.construct(board, port, baudrate);
|
|
|
|
if (!uart->ok)
|
|
{
|
|
base_critical_leave();
|
|
return 1;
|
|
}
|
|
|
|
if (uart->type == Resource::IO_BAR)
|
|
{
|
|
unsigned base = board->get_base(port);
|
|
kuart.access_type = L4_kernel_options::Uart_type_ioport;
|
|
kuart.base_address = base;
|
|
printf("UART IO: @%x\n", base);
|
|
}
|
|
if (uart->type == Resource::MEM_BAR)
|
|
{
|
|
l4_addr_t base = board->get_base(port);
|
|
kuart.access_type = L4_kernel_options::Uart_type_mmio;
|
|
kuart.base_address = base;
|
|
printf("UART MMIO: @%p\n", (void*)base);
|
|
}
|
|
|
|
kuart.base_baud = board->base_baud;
|
|
kuart.baud = baudrate;
|
|
kuart.reg_shift = board->reg_shift;
|
|
|
|
du->set_uart2(uart);
|
|
|
|
kuart.irqno = com_irq;
|
|
kuart_flags |= L4_kernel_options::F_uart_base
|
|
| L4_kernel_options::F_uart_baud;
|
|
if (com_irq != -1)
|
|
kuart_flags |= L4_kernel_options::F_uart_irq;
|
|
|
|
base_critical_leave();
|
|
return 0;
|
|
}
|
|
|
|
void init()
|
|
{};
|
|
|
|
void setup_uart(char const *cmdline)
|
|
{
|
|
const char *s;
|
|
int comport = -1;
|
|
int comirq = -1;
|
|
int pci = 0;
|
|
static Uart_vga _vga;
|
|
static Dual_uart du(&_vga);
|
|
set_stdio_uart(&du);
|
|
|
|
if ((s = check_arg(cmdline, "-comirq")))
|
|
{
|
|
s += 8;
|
|
comirq = strtoul(s, 0, 0);
|
|
}
|
|
|
|
if ((s = check_arg(cmdline, "-comport")))
|
|
{
|
|
s += 9;
|
|
if ((pci = !strncmp(s, "pci:", 4)))
|
|
s += 4;
|
|
|
|
if (pci && !strncmp(s, "probe", 5))
|
|
{
|
|
scan_pci_uarts(&du, 115200);
|
|
reboot();
|
|
}
|
|
|
|
char *ep;
|
|
comport = strtoul(s, &ep, 0);
|
|
if (pci && *ep == ':')
|
|
{
|
|
pci = comport + 1;
|
|
comport = strtoul(ep + 1, 0, 0);
|
|
}
|
|
}
|
|
|
|
if (!check_arg(cmdline, "-noserial"))
|
|
{
|
|
Serial_board board;
|
|
if (pci)
|
|
{
|
|
if (!search_pci_serial_devs(pci - 1, &board))
|
|
{
|
|
legacy_uart(1, comirq, &board);
|
|
comport = 0;
|
|
}
|
|
}
|
|
else if (comport == -1)
|
|
{
|
|
/* try to read Bios Data Area (BDA) to get comport information */
|
|
unsigned short comport_count = (*((unsigned short *)0x410) >> 9) & 0x7;
|
|
if (comport_count) comport = *((unsigned short *)0x400), comirq, &board;
|
|
else comport = 1;
|
|
legacy_uart(comport, comirq, &board);
|
|
comport = 0;
|
|
}
|
|
else
|
|
{
|
|
legacy_uart(comport, comirq, &board);
|
|
comport = 0;
|
|
}
|
|
|
|
if (init_uart(&board, comport, comirq, &du))
|
|
{
|
|
kuart_flags |= L4_kernel_options::F_noserial;
|
|
printf("UART init failed\n");
|
|
}
|
|
}
|
|
else
|
|
kuart_flags |= L4_kernel_options::F_noserial;
|
|
}
|
|
};
|