FOC: Basic Arndale multi-core support
Second CPU is up and receives timer interrupts. Caches are still disabled.
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@@ -25,7 +25,7 @@ set_asid()
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{}
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//---------------------------------------------------------------------------
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IMPLEMENTATION [arm && armv6plus && (mpcore || armca9)]:
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IMPLEMENTATION [arm && armv6plus && (mpcore || armca9 || armca15)]:
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enum
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{
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@@ -33,7 +33,7 @@ enum
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};
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//---------------------------------------------------------------------------
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IMPLEMENTATION [arm && armv6plus && !(mpcore || armca9)]:
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IMPLEMENTATION [arm && armv6plus && !(mpcore || armca9 || armca15)]:
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enum
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{
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